Configurable logic block with AND gate for efficient...

Details Configurable logic block with AND gate for efficient... Configurable logic block with AND gate for efficient...

1997-01-21

2002-07-30

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06427156

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to programmable logic devices having a repeating pattern of logic blocks, and more particularly to an improved logic block therefor.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs) are well known in the art. An FPGA comprises an array of configurable logic blocks (CLBs) which are interconnected to each other through a programmable interconnect structure to provide a logic function desired by a user.
U.S. Pat. No. 4,870,302, reissued as U.S. Pat. No. RE 34,363, and incorporated herein by reference, describes a well known FPGA architecture. Other publications, such as El Gamal's U.S. Pat. No. 4,758,745, Kean's U.S. Pat. No. 5,243,238, and Camarota and Furtek's U.S. Pat. No. 5,245,227, also incorporated herein by reference, describe other FPGA architectures. Pages 4-5 through 4-45 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, also incorporated herein by reference, describe several products which implement a number of FPGA architectures.
An FPGA is a general purpose device, i.e., it is capable of performing any one of a plurality of functions, and is programmed by an end user to perform a selected function. Because of this design flexibility, a general purpose FPGA includes a significant number of wiring lines and transistors, many of which remain unused in any particular application. FPGAs include overhead circuits which facilitate programming of the FPGA to do the specified function. To the extent possible without interfering with required functions, there is a need to conserve overhead chip area by using logic components efficiently. There is a need to minimize both the number of routing lines in a device and the number of logic blocks that must be used to perform a given logic function.
In the aforementioned patent application Ser. No. 08/618,445 now U.S. Pat. No. 5,682,107 of Tavana, Yee and Holen, a CLB is disclosed wherein four lookup table function generators each have four input lines and an output line connected as the control input to a carry chain multiplexer, at least one carry chain multiplexer being associated with each function generator. Each carry chain multiplexer receives a first input from the carry chain (i.e., the output of the prior multiplexer in the serial array of carry chain multiplexers) and a second input from an additional distinct input line to the CLB. The function and structure of a carry chain are described at length in commonly assigned U.S. Pat. No. 5,349,250 to New.
The following drawing conventions are used throughout the figures. A small solid black dot at the intersections of two lines indicates a permanent electrical connection between the crossing lines. An open circle enclosing an intersection between two lines indicates a programmable connection between the lines (for example, a pass transistor, which is turned on to make the connection). Open circles represent bidirectional signal flow between the two lines. An open triangle at an intersection of two lines indicates a programmable connection with signal flow going onto the line pointed to by the apex of the triangle. (The signal is of course then present on the full length of the line. Thus, a triangle pointing in the opposite direction would have the same signal flow because the triangle points to the same wire.) Programmable connections are provided at programmable interconnection points (PIPs), wherein each PIP includes at least one transistor.
A triangle that is on a line but not at an intersection indicates a buffer that produces signal flow in the direction indicated by the apex of the triangle. In
FIG. 3
, except for global lines CLK, CE, RST, TS, ENOUT, and ENLL a line which ends within the tile or matrix structure (i.e., does not extend to the border of the tile or matrix) is physically terminated within the tile. A line which extends to the border of the tile or matrix connects to a line on the next tile, which it contacts when two tiles are abutted together. Note that some lines which extend to an edge of a tile and thus into an adjacent tile change names at the tile boundary.
FIG. 1
shows an FPGA chip
100
in which the CLB of the invention may be employed. In the center portion of chip
100
are a plurality of core tiles
101
, which are interconnected by conductive lines (described in detail below). Chip
100
includes pads, i.e., pads P
1
-P
56
, and input/output blocks (IOBs) for connecting edge tiles
103
,
104
,
105
,
106
, and corner tiles
113
-
116
to external pins of a package that holds chip
100
. Each edge tile and corner tile is further connected to a core tile
101
. Power voltage source pads VCC and ground source pads GND have connections (not shown) in a conventional manner throughout chip
100
.
FIG. 2
shows a core tile
101
. Core tile
101
includes a programmable routing matrix
201
and a CLB matrix
202
. Programmable routing matrix
201
is described in detail by Tavana et al. in related patent application Ser. No. 08/618,445 now U.S. Pat. No. 5,682,107. CLB matrix
202
is described in reference to FIG.
3
and also in detail in the related Tavana et al. patent application.
In
FIG. 2
, CLB matrix
202
is connected to another CLB matrix in a tile to the west (not shown) by output lines Q
0
-Q
3
and input lines QW
0
-QW
3
. CLB matrix
202
connects to a CLB matrix in the tile to the north (not shown) by output lines Q
0
-Q
3
and input lines QN
0
-QN
3
, to a CLB matrix in the east by output lines Q
0
-Q
3
and input lines QE
0
-QE
3
, and to a CLB matrix in the south tile (not shown) by output lines Q
0
-Q
3
and input lines QS
0
-QS
3
. Note that carry-in line CIN and carry-out line COUT, which extend vertically in tile
101
, connect to carry-out and carry-in lines, respectively, in adjacent tiles north and south. Certain labels shown but not discussed in
FIG. 2
are discussed by Tavana et al. in related application Ser. No. 08/618,445 now U.S. Pat. No. 5,682,107 and are shown here for the convenience of the reader.
The carry-in and carry-out lines form a fast carry path for arithmetic functions, as discussed in detail by Bernard J. New in U.S. Pat. No. 5,349,250, entitled “LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY”, which is incorporated herein by reference. Programmable routing matrix
201
is connected in the four directions shown, and additionally connects to CLB matrix
202
. Programmable routing matrix includes a programmable interconnect structure for interconnecting the five sets of incoming lines to each other.
CLB Matrix
202
FIG. 3
illustrates CLB matrix
202
of FIG.
2
. CLB matrix
202
includes a CLB
301
, a tristate buffer block
302
, an input interconnect structure
303
, a CLB output interconnect structure
304
, a feedback interconnect structure
305
, a general input interconnect structure
306
, a register control interconnect structure
307
, an output interconnect structure
308
, and output enable blocks
309
. The structure of
FIG. 3
is described in detail by Tavana et al. in related patent application Ser. No. 08/618,445 now U.S. Pat. No. 5,682,107.
Configurable Logic Block
301
A prior art CLB
301
is illustrated in FIG.
4
. CLB
301
includes four function generators F, G, H, and J. Each function generator comprises a 16-bit lookup table that generates an output signal determined by the four input signals provided to the function generator and the 16 values stored in the lookup table. Thus, function generator F generates an output signal determined by the input signals provided on lines F
0
-F
3
, function generator G generates an output signal determined by the signals provided on CLB input lines G
0
-G
3
, and so on for H and J. This CLB is discussed in detail by Tavana et al. in application Ser. No. 08/618,445, now U.S. Pat. No. 5,682,107 incorporated by reference.
Function generators F, G, H, and J provide output signals on CLB output lines X, Y, Z, and V, respectively. The
FIG. 4
CLB includes a carry chain for fast im

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