Configurable latching for asynchronous memories

Details Configurable latching for asynchronous memories Configurable latching for asynchronous memories

2011-03-29

2011-03-29

Nguyen, Viet (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233170, C365S233100, C365S193000

Reexamination Certificate

active

07916575

ABSTRACT:
A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.

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“Using Intel Flash Memory: Asynchronous Page Mode and Synchronous Burst mode”, Aug. 2004, Intel Application Note 793, pp. 2-28.

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