Configurable DDR write-channel phase advance and delay...

Details Configurable DDR write-channel phase advance and delay... Configurable DDR write-channel phase advance and delay...

2001-08-09

2003-01-07

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06504790

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to phase-shifting capability in a memory device and, more particularly, to configurable phase advance and delay capability in a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
Double data rate (DDR) memory employs a source-synchronous clocking scheme in that a write data strobe (DDR_WDQS) must be propagated from the memory controller to the DDR memory along with the write data mask and write data (DDR_DM/WDBUS). In order for the DDR device to successfully and reliably capture write data, the time between the Write command and the first rising edge of DDR_WRDQS must fall within Tdqss range, which is defined as from 75% to 125% of 1 clock cycle from the Write command. This translates to a ½ cycle window that begins ¾ of a cycle from the cycle on which the Write command was sampled and ends 1 and ¼ of a cycle from the cycle on which the Write command was sampled by the DDR device. Additionally, the write data strobe must be center-aligned with the write data and write data mask, requiring the write data strobe to be delayed by ¼ of a DDR clock cycle with respect to the write data and write data mask. This narrow window is frequency-dependent and decreases as the frequency increases. The delays that affect the DDR_WDQS arrival time include the ASIC I/O driver delay, the board wiring topology and wiring delay, connector loading, and the like. These delays are dependent on process, voltage, and temperature, however they are essentially independent of the frequency of the interface operation.
These frequency-independent fixed delays take up an increasing percentage of the allowable path cycle time and path delay as the frequency increases, making it increasingly difficult to guarantee the aforementioned Tdqss timing requirement. Furthermore, the referenced independent delays may vary from application to application and from system implementation to system implementation. Thus, it becomes very difficult for the design of a single control circuit to satisfy the wide range of possible implementations, particularly as the propagation and circuit delays approach the time allotted for a Tdqss timing window.
Therefore, what is needed is a system and method for adjusting the DDR memory write channel interface timing.
SUMMARY OF THE INVENTION
The present invention provides a memory controller for a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The memory controller comprises a configuration register and a first programmable delay. The first programmable delay receives a first set of one or more bits from the configuration register and a double-speed clock signal. The double-speed-clock signal has a frequency twice as large as the frequency of the internal memory controller clock signal. The memory controller comprises an XOR gate receiving a phase-delayed double-speed clock signal from the first programmable delay and a second set of one or more bits from the configuration register and a first flip-flop (FF) receiving a write command load signal and driven by the internal memory controller clock signal. The memory controller further comprises a first multiplexer receiving the output signal of the first FF and the write command load signal and controlled by a first control signal and a second programmable delay receiving the first set of one or more bits from the configuration register and the output signal of the first multiplexer. The memory controller also comprises more FFs including: a second FF receiving data mask and a low write data (DM/WDATA_L) signal and driven by an inverted signal of the internal memory controller clock signal; a third FF receiving data mask and a high write data (DM/WDATA_H) signal and driven by the internal memory controller clock signal; a fourth FF receiving the output signal of the second programmable delay and driven by the output signal of the first programmable delay; a fifth FF receiving the output signal of the fourth FF and driven by the output signal of the first programmable delay; and a sixth FF receiving the output signal of the fifth FF and driven by the output signal of the first programmable delay. The memory controller further comprises an OR gate receiving the output signal of the fourth FF and the output signal of the sixth FF; a seventh FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; an eighth FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; and a ninth FF receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay. Additionally, the memory controller comprises a second multiplexer receiving the output signal of the seventh FF and the output signal of the ninth FF and controlled by a third set of one or more bits from the configuration register. A tenth FF is also included in the memory controller. The tenth FF receives the output signal of the second multiplexer, outputs a write data strobe (DDR_WDQS), and is driven by the output signal of the XOR gate. The memory controller further comprises a third multiplexer receiving the output signal of the second FF and the output signal of the third FF and controlled by the output signal of the eighth FF. Also, an eleventh FF is included in the memory controller to receive the output signal of the third multiplexer. The eleventh FF is driven by the output signal of the first programmable delay. A fourth multiplexer is included in the memory controller to receive the output signal of the third multiplexer and the output signal of the eleventh FF. The fourth multiplexer is controlled by the third set of one or more bits from the configuration register. Finally, the memory controller comprises a twelfth FF receiving the output signal of the fourth multiplexer, outputting a write data mask and write data (DDR_DM/WDBUS) signal, and driven by the output signal of the XOR gate.


REFERENCES:
patent: 5559751 (1996-09-01), Trinberger
patent: 5822255 (1998-10-01), Uchida
patent: 5923613 (1999-07-01), Tien et al.
patent: 6178123 (2001-01-01), Kato et al.

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