Configurable data width direct memory access device with a read

Details Configurable data width direct memory access device with a read Configurable data width direct memory access device with a read

1990-10-09

1994-07-26

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 395500, 364DIG1, 3642384, 3642403, 3642423, 36424231, G06F 1328, G06F 1200

Patent

active

053332946

ABSTRACT:
A system where counters which increment based on a desired data transfer width are used to control addresses provided to memory devices. Transceivers are located on each byte lane between the system data bus and the internal data bus, with copy transceivers connected between the various byte lanes of the internal bus. The various devices are controlled so that data can be transferred in one, two or four byte increments and yet the memory devices are fully utilized. Separate counters are used for read and write directions. Circuitry is used to determine system memory data width and addressing format so that the desired data transfer width can be determined and set to allow the highest possible data transfer rate.

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Monolithic Memories, LSI data book, 7th edition; First-In First-Out (FIFO) Cascadable Memory, pp. 8-19 to 8-29, 1986.
Monolithic Memories, data sheet on FIFI RAM Controller, 1986.

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