Configurable data converter

Details Configurable data converter Configurable data converter

1999-06-24

2001-07-03

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Reexamination Certificate

active

06255972

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to analog-to-digital (A/D) and digital-to-analog (D/A) converters. More particularly, it relates to an improved architecture design including a configurable embedded data converter.
2. Background of Related Art
Many, many digital devices are utilized by consumers throughout the world. Many of these digital devices translate or convert an analog signal into a digital signal, and/or a digital signal back into an analog signal. For instance, compact disk (CD) players convert a digital signal read from a CD back into an analog signal for audible output by speakers. Moreover, telephone equipment such as digital cordless telephones and digital telephone answering devices convert between an analog signal (e.g., from a microphone) into a digital signal for digital transmission from a remote handset to a base unit (digital cordless telephone) or for digital storage in appropriate non-volatile memory (telephone answering device).
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a “codec.” A codec (short for
CO
der-
DEC
oder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality audio capability, today's codecs find practical application in consumer stereo equipment including CD players, modems, computers and digital speakers.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. Improved S/N ratios have been achieved largely by separating the conventional codec into two individual sub-systems and/or two separate integrated circuits (ICs): a controller sub-system handling primarily the digital interface to a host processor, and an analog sub-system handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the “Audio Codec '97 Component Specification”, Revision 1.03, Sep. 15, 1996, as revised in “Audio Codec '97”, Revision 2.0, Sep. 29, 1997 (collectively referred to herein as “the AC '97 specification”). The AC '97 specification in its entirety is expressly incorporated herein by reference.
FIG. 5
is a generalized block diagram of a conventional split-architecture audio codec conforming to the AC '97 specification. Audio codecs conforming to the AC '97 specification accommodate audio sources from CD players, auxiliary devices such as stereo equipment, microphones and/or telephones.
As shown in
FIG. 5
, currently known split-architecture audio codecs contemplate a host processor, an audio codec (AC) controller sub-system or IC
402
, and an AC analog sub-system or IC
404
. The connection between the AC controller sub-system
402
and the AC analog sub-system
404
is currently defined as a five-wire time division multiplexed (TDM) interface controlled by an AC-link
406
in the AC analog sub-system
404
. The AC link
406
includes one serial output data line and one serial input data line, both synchronized to a frame pulse synchronization signal.
The AC controller sub-system
402
may be a stand alone device, or it may be a portion of a larger device such as a Peripheral Component Interconnect (PCI) interface device. PCI is a processor-independent, self-configuring local bus. Alternatively, the AC controller sub-system
402
may be a part of a central processing unit (CPU).
Because of the capabilities of the split digital/analog architecture (i.e., AC controller sub-system
402
and AC analog subs system
404
), the AC '97 specification includes a significant amount of flexibility intended to capture a large market by satisfying many consumer-related audio needs. For instance, the conventional AC analog sub-system
404
includes interface capability to accept input from multiple sources and to mix the analog signals from those multiple sources. Possible analog signal sources include a CD, video, or telephone line.
FIG. 6
is a diagram showing relevant features of the conventional AC analog sub-system
404
.
In particular,
FIG. 6
shows a conventional brute force use of as many of a plurality of digital-to-analog (D/A) converters
204
a,
204
b
and a plurality of analog-to-digital (A/D) converters
206
a
-
206
c
are needed to convert between analog signals used by the analog mixing and gain control module
200
and the digital interface
202
. The designer in such a system determines beforehand the maximum number of D/A and/or A/D converters necessary to fulfill the particular application, and then implements that number of separate D/A and or A/D converters in a suitable device.
The AC link
406
includes input and output time division multiplexed (TDM) serial data lines, each including “time slots” for use by a particular D/A or A/D converter. The D/A converters
204
a,
204
b
input from respective appropriate time slots of an input TDM serial line of the AC link 406, while the A/D converters
206
a
-
206
c
output to respective appropriate time slots of an output TDM serial line of the AC link
406
.
The TDM serial lines are synchronized into data frames, each data frame containing a plurality of time slots. For instance, a particular data frame may refresh every 256 cycles of a data clock (e.g., a 4 MHz data clock). The frames are conventionally synchronized with a frame synchronization signal or similar signal.
Depending upon the bit length of the data samples output from the AND converters
206
a
-
206
c,
and/or upon the bit length of the data samples input to the D/A converters
204
a,
204
b,
each data frame is conventionally designed to contain fixed locations for data samples from each of the A/D and D/A converters. Thus, based on a designed configuration, conventional input and output TDM serial data streams for embedded converters have fixed locations within a data frame based on maximum sample lengths.
Unfortunately, to change such systems having fixed time slot configurations for A/D and/or D/A input and output with respect to the data frame synch signal, the embedded circuit must be redesigned with the development of a new chip. For instance, to add an A/D and/or D/A channel beyond those previously included in a device, or to increase the sample length of a particular converter beyond its previous maximum expected length, additional space for additional components, reconfiguration of time slots, and/or additional power consumption will be required.
There is thus a need for a more flexible architecture allowing the addition of new A/D and/or D/A data channels, and/or the increase in sample lengths, in an embedded converting system without the need to reengineer and/or re-manufacture the component to accommodate the change, and/or the increase in sample lengths.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, an embedded digital system comprises a data converter, and a converter configuration register adapted to changeably define a conversion mode of the data converter on a bitwise basis with respect to a data frame.
A method of selectably configuring a serial data frame including a plurality of conversion data comprises setting a conversion mode of a data converter for a particular one of a plurality of conversions performed by the data converter, and defining a location for an output of the particular conversion in the data frame.


REFERENCES:
patent: 4609906 (1986-09-01), Wiegel

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