Configurable clock network for programmable logic device

Details Configurable clock network for programmable logic device Configurable clock network for programmable logic device

2006-07-11

2006-07-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

C327S297000

Reexamination Certificate

active

07075365

ABSTRACT:
In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3997874 (1976-12-01), Kelly et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4542509 (1985-09-01), Buchanan et al.
patent: 4633488 (1986-12-01), Shaw
patent: 4658152 (1987-04-01), Walters
patent: 4719593 (1988-01-01), Threewitt et al.
patent: 4857866 (1989-08-01), Tateishi
patent: 4868522 (1989-09-01), Popat et al.
patent: 4959646 (1990-09-01), Podkowa et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5075575 (1991-12-01), Shizukuishi et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5121014 (1992-06-01), Huang
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5208557 (1993-05-01), Kersh
patent: 5239213 (1993-08-01), Norman et al.
patent: 5349544 (1994-09-01), Wright et al.
patent: 5394116 (1995-02-01), Kasturia
patent: 5397943 (1995-03-01), West et al.
patent: 5418499 (1995-05-01), Nakao
patent: 5420544 (1995-05-01), Ishibashi
patent: 5424687 (1995-06-01), Fukuda
patent: 5448191 (1995-09-01), Meyer
patent: 5477182 (1995-12-01), Huizer
patent: 5506878 (1996-04-01), Chiang
patent: 5535240 (1996-07-01), Carney et al.
patent: 5542083 (1996-07-01), Hotta
patent: 5581214 (1996-12-01), Iga
patent: 5586307 (1996-12-01), Wong et al.
patent: 5629651 (1997-05-01), Mizuno
patent: 5642082 (1997-06-01), Jefferson
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5656959 (1997-08-01), Chang et al.
patent: 5691669 (1997-11-01), Tsai et al.
patent: 5699020 (1997-12-01), Jefferson
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5744991 (1998-04-01), Jefferson et al.
patent: RE35797 (1998-05-01), Graham et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5847617 (1998-12-01), Reddy et al.
patent: 5889436 (1999-03-01), Yeung et al.
patent: 5900757 (1999-05-01), Aggarwal et al.
patent: 5952891 (1999-09-01), Boudry
patent: 5963069 (1999-10-01), Jefferson et al.
patent: 5970110 (1999-10-01), Li
patent: 5974105 (1999-10-01), Wang et al.
patent: 5987543 (1999-11-01), Smith
patent: 5999025 (1999-12-01), New
patent: 6014048 (2000-01-01), Talaga, Jr. et al.
patent: 6020931 (2000-02-01), Bilbrey et al.
patent: 6043677 (2000-03-01), Albu et al.
patent: 6058117 (2000-05-01), Ennamorato et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6069507 (2000-05-01), Shen et al.
patent: 6072348 (2000-06-01), New et al.
patent: 6081022 (2000-06-01), Mitra et al.
patent: 6104222 (2000-08-01), Embree
patent: 6114915 (2000-09-01), Huang et al.
patent: 6125217 (2000-09-01), Paniccia et al.
patent: 6125421 (2000-09-01), Roy
patent: 6127865 (2000-10-01), Jefferson
patent: 6141394 (2000-10-01), Linebarger et al.
patent: 6144224 (2000-11-01), Lee et al.
patent: 6144242 (2000-11-01), Jeong et al.
patent: 6157266 (2000-12-01), Tsai et al.
patent: 6188699 (2001-02-01), Lang et al.
patent: 6195758 (2001-02-01), Lundh et al.
patent: 6229861 (2001-05-01), Young
patent: 6249189 (2001-06-01), Wu et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6278332 (2001-08-01), Nelson et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6320469 (2001-11-01), Friedberg et al.
patent: 6326812 (2001-12-01), Jefferson
patent: 6359483 (2002-03-01), Watkins et al.
patent: 6369624 (2002-04-01), Wang et al.
patent: 6373278 (2002-04-01), Sung et al.
patent: 6411150 (2002-06-01), Williams
patent: 6462623 (2002-10-01), Horan et al.
patent: 6463547 (2002-10-01), Bailey et al.
patent: 6483886 (2002-11-01), Sung et al.
patent: 6504415 (2003-01-01), Robinson et al.
patent: 6650161 (2003-11-01), Thomas et al.
patent: 6730540 (2004-05-01), Siniaguine
patent: 6862548 (2005-03-01), Chan
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2005/0080580 (2005-04-01), Kantake
patent: 0 266 065 (1988-05-01), None
patent: 0 416 930 (1991-03-01), None
patent: 0 501 652 (1992-09-01), None
patent: 0 657 797 (1995-06-01), None
patent: 0 778 517 (1997-06-01), None
patent: 0 903660 (1999-03-01), None
patent: 0 987 822 (2000-03-01), None
patent: 1 056 207 (2000-11-01), None
patent: 0 657 797 (2003-07-01), None
patent: 1-137646 (1989-05-01), None
patent: 10215156 (1998-08-01), None
patent: WO 91/10951 (1991-07-01), None
Advanced Micro Devices, Inc., “Am2971 Programmable Event Generator (PEG),” Publication No. 05280, Rev. C, Amendment /0, pp. 4-286-4-303 (Jul. 1986).
Advanced Micro Devices, Inc., “AmPAL *23S8 20-Pin IMOX PAL-Based Sequencer,” Publication No. 06207, Rev. B, Amendment /0, pp. 4-102-4-121 (Oct. 1986).
Agere Systems, Inc., “ORCA ORT82G5 0.622/1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC,” Preliminary Data Sheet, pp. 1-35 (Jul. 2001).
Agere Systems, Inc., “ORCA 8850 Field-Programmable System Chip (FPSC) Eight Channel x 850 Mbits/s Backplane Transceiver,” Product Brief, pp. 1-6 (Jul. 2001).
Agere Systems, Inc., “ORCA 8850 Field-Programmable System Chip (FPSC) Eight Channel x 850 Mbits/s Backplane Transceiver,” Product Brief, pp. 1-36 (Aug. 2001).
DynaChip Corp., “Application Note: Using Phase Locked Loops in DL6035 Devices” (1998).
DynaChip Corp., DY6000 Family Datasheet (Dec. 1998).
Ko, U., et al., “A 30-ps Jitter, 3.6 μs Locking, 3.3-Volt Digital PLL for CMOS Gate Arrays,”Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, Publication No. 0-7803-0826-3/93, pp. 23.3.1-23.3.4 (May 9-12, 1993).
LSI Logic Corp., 500K Technology Design Manual (Document DB04-000062-00, First Edition), pp. 8-1-8-33 (Dec. 1996).
Lucent Technologies, Inc., Optimized Reconfigurable Cell Array (ORCA®) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, (Nov. 1997).
Lucent Technologies, Inc., ORCA® Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01 (Aug. 1998).
Monolithic Memories, Inc., “Programmable Array Logic PAL20RA10-20 Advance Information,” pp. 5-95-5-102 (Jan. 1988).
National Semiconductor Corp.,LVDS Owner's Manual&Design Guide(Apr. 25, 1997).
National Semiconductor Corp., “DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHZ,” (Mar. 1998).
Xilinx, Inc., Virtex 2.5V Field Programmable Gate Arrays Advance Product Specification (Version 1.0) (Oct. 20, 1998).
Xilinx, Inc., Application Note: Using the Virtex Delay-Locked Loop (Version 1.31) (Oct 21, 1998).
Zaks, R., et al.,From Chips to Systems: An Introduction to Microcomputers, pp. 54-61 (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1987).
Application Note AN259, Avriohoca, K., “Applications and Performance of PTN1111 and PTN2111 Clock Distribution Devices,” Philips Semiconductors, Oct. 16, 2001, pp. 1-6.
Blair, G. M., “Self Generating Clock Using an Augmented Distribution Network,” IEE Proc. Circuits Devices Syst., vol. 144, No. 4, Aug. 1997, pp. 219-222.
Chen, Y., et al., “The Associative-Skew Clock Routing Problem,” 1999 IEEE/ACM International Conference on Computer-Aided Design; Digest of Technical Papers, Nov. 7-11, 1999, pp. 168-172.
Debaes, C., et al., “Receiver-Less Opt

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