Configurable central memory buffered packet switch module...

Details Configurable central memory buffered packet switch module... Configurable central memory buffered packet switch module...

2005-06-28

2010-12-21

Patel, Jayanti K (Department: 2465)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S413000, C370S422000

Reexamination Certificate

active

07856026

ABSTRACT:
Modules and methods are described for buffering packets to be switched in a system, such as a programmed device. The modules can be configured for different packet lengths, protocols, applications, and/or designs in a larger system. Techniques and mechanisms are further described for implementing a central memory and a linked-list addressing scheme. Accordingly, memory blocks of the central memory can be used for variable length packets and further reused at substantially the same time as they become available, thereby improving packet switching efficiency and/or flexibility.

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Altera®, Atlantic Interface, Functional Specification 13, Jun. 2002, ver. 3.0, pp. 1-10.

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