Configurable cellular array

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3074651, H03K 19173

Patent

active

052432386

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a configurable cellular array consisting of an array of dynamically configurable logic elements, that is logic elements in which the function realised is dependent on an associated single word of control memory, rather than physical wires connected between logic elements.
Configurable logic elements and circuits formed therefrom have been studied for many years. Configurable logic is distinct from microprogramming in that a single long control word is established to control a hardware unit, rather than a sequence of short control words selected from many words in a memory by a sequencer. Normally the hardware unit is significantly more complex in the case of configurable logic. The implementation of the two types is also radically different in configurable logic. The control and function are intermingled in a single structure whereas in microprogramming the control is provided by a separate unit.
One family of configurable circuits, cellular arrays, as disclosed in a paper entitled "A Survey of Microcellular Research" by R Minnick., J.ACM, 14 (2); 203-241, Published April 1967, have been of particular interest. Most cellular array designs have their function fixed by making or breaking physical wires on an integrated circuit as in conventional logic means, although a system where the function is dependent on a control memory is described in a publication by Richard G Shoup. Richard G Shoup. Programmable Cellular Logic Arrays. PhD thesis, Computer Science Dept., Carnegie-Mellon University, March 1970.
Existing programmable cellular arrays suffer from a lack of functional generality caused by limited routing options provided in each cell and because these designs considered relatively small systems where the entire array was contained in a single chip or built of many chips each containing one or a small number of cells. One reason for this is that these designs are intended to implement subsystems, for example single or multiple output logic functions of several input variables, rather than complete systems. Thus the lack of flexibility in each cell and the total number of cells available limits the functional generality available. To take advantage of the potentially very large number of flexible cells which can be implemented on a single chip or a multi-chip array with current processing technology, and to allow complete systems of the size currently implemented as application specific integration circuits to be designed with a programmable structure, a more flexible architecture is required. To allow such multi-chip arrays to be built where relatively large numbers of cells are present on each chip such a system must be capable of transferring large numbers of input/output signals between chips.
It is an object of the present invention to provide an improved configurable cellular array which obviates or mitigates at least one of the aforementioned disadvantages.
This is achieved by provided a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least one bit wide to each of its neighbours, and each cell having a programmable routing unit to permit selective intercellular connections to be made.
In a preferred arrangement each cell contains a programmable function unit which includes a plurality of multiplexors. In a preferred arrangement the function unit and routing unit are programmable using associated Random Access Memory (RAM) areas within the cell. Each cell may be coupled to at least one global or array-crossing signal so that all cells can be signalled simultaneously. The 2-dimensional array is rectangular and the intercell connections are orthogonal and are one bit wide.
Accordingly in one aspect of the present invention there is a 2-dimensional configurable cellular array comprising a plurality of configurable cells, each cell having a plurality o cell inputs and a plurality of cell outputs;
each cell being connected to each of its neighbouring cells only in the array by one of said cell inputs and one of s

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