Config logic power saving method

Details Config logic power saving method Config logic power saving method

2008-07-03

2009-11-10

Tan, Vibol (Department: 2819)

Static information storage and retrieval

Powering

Conservation of power

C365S228000, C365S229000, C713S320000, C713S323000, C713S324000

Reexamination Certificate

active

07616517

ABSTRACT:
A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.

REFERENCES:
patent: 6924663 (2005-08-01), Masui et al.
patent: 7319343 (2008-01-01), Bhunia et al.
patent: 7562275 (2009-07-01), Juhn et al.

Affiliated with

Also associated with

Rating

Config logic power saving method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Config logic power saving method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Config logic power saving method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4130794