Conductor structure for a magnetic memory

Details Conductor structure for a magnetic memory Conductor structure for a magnetic memory

2002-04-25

2003-07-22

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S422000, C257S428000, C257S775000

Reexamination Certificate

active

06597049

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a conductor structure for a magnetic memory device. More specifically, the present invention relates to a conductor structure for a magnetic memory device in which a cross-sectional area of a conductor is decreased to increase a current density in the conductor or in which the cross-sectional area is increased to reduce a resistance to a flow of electrons in the conductor and the conductor is partially cladded to increase a magnetic field such that a reduced amount of current is required to write a bit of data to the magnetic memory device.
BACKGROUND OF THE ART
Magnetic Random Access Memory (MRAM) is an emerging technology that can provide an alternative to traditional data storage technologies. MRAM has desirable properties including fast access times like DRAM and non-volatile data retention like hard disc drives. MRAM stores a bit of data (i.e. information) as an alterable orientation of magnetization in a patterned thin film magnetic element that is referred to as a data layer, a storage layer, or a data film. The data layer is designed so that it has two stable and distinct magnetic states that define a binary one (“1”) and a binary zero (“0”). Although the bit of data is stored in the data layer, many layers of carefully controlled magnetic and dielectric thin film materials are required to form a complete magnetic memory element. One prominent form of magnetic memory element is a spin tunneling device. The physics of spin tunneling is complex and good literature exits on this subject.
In
FIG. 1
a
, a prior MRAM memory element
101
includes a data layer
102
and a reference layer
104
that are separated by a thin barrier layer
106
. Typically the barrier layer
106
has a thickness that is less than about 2.0 nm. The memory element
101
has a width W and a height H and a ratio of the width W to the height H defines an aspect ratio (i.e. aspect ratio=W÷H). In a tunneling magnetoresistance (TMR) structure the barrier layer
106
is an electrically non-conductive dielectric material such as aluminum oxide (Al
2
O
3
), for example. Whereas, in a giant magnetoresistance (GMR) structure the barrier layer
106
is a thin layer of conductive material such as copper (Cu), for example. The reference layer
104
has a pinned orientation of magnetization
108
, that is, the pinned orientation of magnetization
108
is fixed in a predetermined direction and does not rotate in response to an external magnetic field. In contrast the data layer
102
has an alterable orientation of magnetization
103
that can rotate between two orientations in response to an external magnetic field.
In
FIG. 1
b
, when the pinned orientation of magnetization
108
and the alterable orientation of magnetization
103
point in the same direction (i.e. they are parallel to each other) the data layer
102
stores a binary one (“1”). On the other hand, when the pinned orientation of magnetization
108
and the alterable orientation of magnetization
103
point in opposite directions (i.e. they are anti-parallel to each other) the data layer
102
stores a binary zero (“0”).
In
FIG. 2
, the prior memory element
101
is typically positioned at an intersection of two orthogonal conductors
105
and
107
. For instance, the conductor
105
can be a word line and the conductor
107
can be a bit line. A bit of data is written to the memory element
101
by generating two magnetic fields H
X
and H
Y
that are in turn generated by currents I
Y
and I
X
flowing in the conductors
107
and
105
respectively. The magnetic fields H
X
and H
Y
cooperatively interact with the data layer
102
to rotate the alterable orientation of magnetization
103
from its current orientation to a new orientation. Therefore, if the current orientation is parallel (i.e. positive x-direction on the x axis) with the pinned orientation of magnetization
108
such that a binary “1” is stored in the data layer
102
, then the magnetic fields H
X
and H
Y
will rotate the alterable orientation of magnetization
103
to an anti-parallel orientation (i.e. negative x-direction on the x axis) such that a binary “0” is stored in the data layer
102
.
In
FIG. 3
, the prior memory element
101
is positioned in a large array
201
of similar memory elements
101
that are also positioned at an intersection of a plurality of the conductors
107
and
105
that are arranged in rows and columns. For purposes of illustration, in
FIG. 3
, the conductors
107
are bit lines and the conductors
105
are word lines. The conductors (
105
,
107
) need not be in direct contact with the memory element
101
. Typically, one or more layers of material separate the conductors (
105
,
107
) from the data layer
102
and the reference layer
104
.
A bit of data is written to a selected one of the memory elements
101
that is positioned at an intersection of a word and bit line by passing the currents I
Y
and I
X
through the word and bit lines. During a normal write operation the selected memory element
101
will be written to only if the combined magnetic fields H
X
and H
Y
are of a sufficient magnitude to switch (i.e. rotate) the alterable orientation of magnetization of the memory element
101
.
One disadvantage of the prior memory element
101
is that the conductors
107
and
105
have a nominal thickness denoted as t
N
and a width W
B
and W
W
respectively that are substantially equal to the width W and height H of the memory element
101
. In
FIG. 4
, a cross-sectional view of the memory element
101
along the y-axis Y illustrates the conductor
107
as having a width W
B
that is substantially equal to the width W of the memory element
101
. Similarly, a cross-sectional view of the memory element
101
along the x-axis X illustrates the conductor
105
as having a width W
W
that is substantially equal to the height H of the memory element
101
.
As a result of the above mentioned thicknesses t
N
and widths (W
B
and W
W
), the magnitude of the currents I
Y
and I
X
required to generate the combined magnetic fields H
X
and H
Y
is high. There are several disadvantages to high currents. First, the transistor driver circuits for sourcing those currents are sized based on the amount of current required. Consequently, higher currents require larger driver circuits. As the dimensions of the memory elements
101
shrink to increase areal density, it is desirable to also shrink the size of the driver circuits so that the amount of area occupied by the array
201
is minimized.
Second, in portable electronics applications where the power source is typically a battery, high current demands result in a reduction in battery life and can require larger and heavier batteries. It is desirable to reduce weight, size, and to increase battery life for longer operating times.
Finally, in low power applications, the waste heat generated by a microelectronic device is proportional to the amount of current supplied. Therefore, waste heat generation increases with higher current demands. Excessive waste heat generation can elevate the temperature of the device, often with deleterious effects.
U.S. Pat. No. 6,236,590 to Bhattacharyya et al., discloses a conductor layout structure in which the amount of current required to switch the data layer is reduced by reducing the width of the conductors such that the edges of the conductors are within the width or the length of the memory element in the direction the conductor crosses the memory element. However, further reductions in current are required as the dimensions of magnetic memory elements continue to shrink. Therefore, there is room for further reductions in current consumption during write operations in MRAM devices.
Consequently, there exists a need for a conductor structure for a magnetic memory cell that provides optimal use of current to switch the data layer of the memory cell. There is also a need for a conductor structure for a magnetic memory cell that uses the available current more efficiently than the pri

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