Conductor structure

Details Conductor structure Conductor structure

2000-01-28

2001-07-10

Reichard, Dean A. (Department: 2831)

Electricity: conductors and insulators

Anti-inductive structures

Conductor transposition

Reexamination Certificate

active

06259018

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a conductor structure for timing signals, and more particularly but not exclusively to such a structure in an integrated circuit.
BACKGROUND OF THE INVENTION
The high complexity of modern integrated circuits means that large amounts of information are capable of being handled. The processing which takes place in integrated circuits is typically performed in response to control signals, such as clock signals, and the high speed of processing which is currently being achieved makes it important that such control signals are transferred in the minimum possible time.
Those skilled in the art will appreciate that different control signals may need to be transmitted over respective conductors which are closely adjacent to one another, and it is therefore clearly a desirable feature to reduce as far as possible any cross-talk between adjacent conductors.
The cross-talk between adjacent conductors can be quantified by the inter-conductor capacitance.
It will be further clear to those skilled in the art that a major factor in the efficiency of an integrated circuit is the performance of the longest conductor of a set carrying control signals, because the propagation time along the longest conductor of a set will clearly be the longest.
It is an object of the present invention to provide an improved conductor structure.
It is an aim of embodiments of the invention to provide a wiring structure in which the capacitance of a longest of the conductors with respect to the other conductors of the set is reduced.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a wiring structure for timing signals comprising at least three spaced conductors having portions disposed substantially parallel to each other, said portions being of different lengths and comprising a longest said portion and a shortest said portion, wherein the longest said portion forms one extreme side of said wiring structure and the shortest said portion is disposed next to the longest said portion whereby delay in the conductor to which said longest portion belongs, said delay being due to cross-talk with others of said conductors, is reduced.
Preferably said portions further comprise a next longest said portion, said next longest said portion being disposed next to the shortest said portion.
According to a second aspect of the present invention there is provided a wiring structure for timing signals comprising at least three conductors and a corresponding number of terminals, each said conductor having a respective first portion, said first portions running substantially mutually parallel on a first planar path, and a respective second portion, said second portion running substantially mutually parallel on a second planar path from said first path to the terminals, wherein at least one pair of conductors which are mutually adjacent on said first path are separated on said second path by at least one other of said conductors.
According to a third aspect of the present invention there is provided a wiring structure for timing signals, comprising at least three conductors and a corresponding number of terminals, said conductors each having a respective first portion, said first portions running substantially mutually parallel on a first planar path and a respective second portion, said second portions running substantially mutually parallel on a second planar path from said first path to the terminals, wherein said terminals are disposed such that the lengths of the second portions of said conductors differ, and said conductors comprise a first conductor having a longest second portion and a second conductor having a next longest second portion, said first and said second conductors being adjacent along said first path and in said second path being disposed such that a second portion of at least one other of said conductors is between said first and second conductors.
Preferably the second planar path is substantially perpendicular to the first planar path.
Preferably the plane of the first planar path does not intersect the plane of the second planar path.


REFERENCES:
patent: 5288949 (1994-02-01), Crafts
patent: 5618185 (1997-04-01), Aekins
patent: 5811727 (1998-09-01), Lo
patent: 6107578 (2000-08-01), Hashim
patent: 8 101854 (1996-04-01), None
Standard Search Reports dated Mar. 9, 1999.
Patent Abstracts of Japan vol. 016, No. 570 (E-1297), Dec. 10, 1992 & JP 04 221837 Aug, 12, 1.

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