Conductor posts, construction for and method of fabricating...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S107000, C438S612000

Reexamination Certificate

active

06706554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a construction for forming conductor posts on each electrode pad of a semiconductor integrated circuit chip (hereinafter referred to as IC chip) and a method of fabricating the same, particularly to a construction for connecting between the IC chips by use of the conductor posts.
2. Description of the Related Art
There have been conventionally required IC chips which performs more complicated functions at higher speed while microfabricated, particularly there has been required a technique for reducing a chip package size while enhancing the performance of bare chips to pursue the microfabrication of the chips. A CSP (chip size package) has been particularly put into importance because it can be mounted on a printed board with dimensions close to a bare chip size, while a high density miniaturized package can be fabricated, and the performance of the chips can be frequently improved.
It is possible to fabricate the CSP by a variety of fabrication methods. However, even if an IC chip such as a CSP and the like is fabricated by either fabricating method, if the connection parts of the IC chip such as a CSP and the like are small, patterning cannot be effected, and electrodes of the IC chip cannot be aligned with the printed board, and the like when the chip is electrically connected to the printed board, and hence the connection parts have to secure the dimensions of certain size. Accordingly, a re-wiring layer or a pad re-layout has to be provided on the IC chip such as a CSP so as to form connection electrodes having dimensions needed for an external printed board.
Concretely, for example, with a method of fabricating a CSP in a chip level typically represented by a &mgr;BGA, a TAB tape
124
having an elastomer
120
serving as an elastic body provided with inner leads
122
is fixed to an integrated circuit board
150
, then solder balls
126
each serving as an electrode are formed (See FIG.
29
A).
With a method of fabricating a CSP in a wafer level which is an assembly technique in a state of wafer, after metal posts
128
and plastic molding are formed, solder balls
126
each serving as an electrode are formed (See FIG.
29
B). Further, as shown in
FIG. 29C
, there is a method of forming a bump
130
by a metal plating instead of solder balls.
Further, with a method of fabricating a CSP in a wafer level, an S-shaped microspring
132
serving as an electrode is formed on the wafer by an Au wire while a wire bonding technique is applied thereto (See FIG.
29
D).
With the foregoing methods, as shown in
FIG. 29E
, the sum of an area B of electrode pads at the periphery of the IC chip and an area of active parts of the IC becomes an area of the IC chips. However, there are following problems in the conventional method of fabricating the IC chips.
First of all, with a method of fabricating the CPS in a chip level as shown in
FIG. 29A
, the formation of the re-wiring layer electrode pads is needed to use solder balls for connecting between the solder balls and active parts of the IC, but the electrode pads have to require a largeness to some extent because the size of each solder ball is large. As a result, the dimensions of electrode parts of the IC chip are not particularly microfabricated, causing a problem that the IC chip is difficult to be microfabricated as a whole. In addition to that, there is another problem that fabricating steps increase because the formation of the re-wiring layer and re-wiring layer electrode pads are required.
Further, with a method of fabricating the CSP in a wafer level as shown in
FIG. 29B
, elements having solder balls which are mechanically formed in advance are handled as individual parts, and also the size of each solder ball is large so that each electrode pad requires a largeness to some extent, resulting in the difficulty of microfabrication. In addition to that, since the solder balls directly contact the printed board, when the solder balls are connected to an external printed board, they are prone to be broken owing to mutual stresses. This is the same in the case of application of metal plating (See FIG.
29
C).
Still further, with a method of bonding a metal wire that is a so-called microspring as shown in
FIG. 29D
, it is difficult to microfabricate the chip because the minimum pitch capable of forming the microspring is about 140 &mgr;m.
Even with the IC chips fabricated in either method, an area which an in depth probe contacts requires some extent (to the extent of 100 to 60 &mgr;m), causing a problem of limits of microfabrication of each electrode pad.
The invention has been made for solving the foregoing problems, and it is an object of the invention to microfabricate each electrode pad, thereby providing an IC chip and a printed board, and a method of fabricating them.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, each conductive metal post is formed on the surface of each electrode pad serving as an input/output terminal of an IC chip. Since the metal post is directly formed on each electrode pad without intervening a re-wiring layer therebetween, it is not necessary to form the re-wiring layer when the electrode pad is formed. Accordingly, it is not necessary to consider the size of the re-wiring layer, thereby microfabricating the electrode pad to eventually microfabricate the IC chip as a whole. Further, since the electrode pads are microfabricated, if they are disposed on the active parts of the IC, they do not interfere with the IC, and hence the electrode pad can be also disposed on the active parts of the IC. Accordingly, the IC chip can be microfabricated. Meanwhile, the metal post can be formed directly on the IC chip without intervening the electrode pad therebetween as the case may be.
The metal post can be formed using an IC technique such as a photolithography, etching, and the like. The metal post need not be made of one metallic material but may be made of a plurality of metallic materials in a lamination. Further, a solder bump can be provided on the tip end of the metal post, and the solder bump may be formed utilizing an IC technique such as photolithography, etching, and the like, and also may be formed by dipping the metal post in a solder bath, or a plating bath and the like.
According to a second aspect of the invention, with the foregoing IC chip, the tip end of the metal post is formed in a configuration wherein a capillary phenomenon occurs relative to a molten electric connection material.
For the configuration in which the capillary phenomenon occurs, it is formed by rendering the tip end of the metal post, for example, to be in irregularities, or concave or convex. As a result, when the tip end of the metal post is dipped in, for example, a solder bath or a plating bath, molten solder or plating liquid enters concaves of the irregularities, and hence surface tension occurs to solder or plating liquid therearound. Accordingly, the solder bump can be easily formed at the tip end of the metal post.


REFERENCES:
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5075965 (1991-12-01), Carey et al.
patent: 5791552 (1998-08-01), Werther
patent: 5926731 (1999-07-01), Coapman et al.
patent: 6028357 (2000-02-01), Moriyama et al.
patent: 6177329 (2001-01-01), Pang
patent: 6376374 (2002-04-01), Stevens
patent: 2002/0121692 (2002-09-01), Lee et al.
patent: 10-064953 (1998-03-01), None

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