Conductor arrangement for reduced noise differential signalling

Details Conductor arrangement for reduced noise differential signalling Conductor arrangement for reduced noise differential signalling

2006-01-10

2006-01-10

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C324S761010

Reexamination Certificate

active

06985820

ABSTRACT:
A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality which includes constructing an array of pins, arranging a plurality of differential pairs within the array of pins to provide a pin arrangement, exciting each of the differential pairs within the pin arrangement, monitoring coupled noise on other differential pairs within the pin arrangement, and analyzing the pin arrangement based upon the monitoring.

REFERENCES:
patent: 5065090 (1991-11-01), Gheewala
patent: 5486766 (1996-01-01), Hibdon et al.
patent: 5596269 (1997-01-01), Miller et al.
patent: 6100815 (2000-08-01), Pailthorp
patent: 6198297 (2001-03-01), Riccioni
patent: 6933853 (2005-08-01), Barr et al.
patent: 2004/0249585 (2004-12-01), Barr et al.

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