Patent
1987-07-27
1989-07-25
LaRoche, Eugene R.
357 238, 357 38, H01L 2978, H01L 2974
Patent
active
048518883
ABSTRACT:
The MOS-FET includes a semiconductor substrate of a first conductivity type functioning as a drain layer; first base layer of a second conductivity type formed on the substrate; second base layer of the first conductivity type which is formed on a surface of the first base layer and which has a portion which forms a channel region surface where an inversion layer is formed between the source layer and the first base layer; a source layer of the second conductivity type formed on the second base layer; a gate oxidation film which is formed on the source layer, the second base layer and the first base layer and which has a thick oxidation film portion covering a portion of the channel region surface and a thin oxidation film portion covering an active portion of the MOS-FET; and a gate polysilicon layer formed on a surface of one of (i) the thin oxidation film portion and (ii) the thin oxidation film portion and the thick oxidation film portion, such that the thick oxidation film portion is disposed between the channel region portion where the inversion layer is formed and the gate polysilicon layer, so as to prevent the inversion layer from being produced in the portion of the channel region surface which is covered by the thick oxidation film portion.
REFERENCES:
patent: 4631564 (1986-12-01), Neilson et al.
patent: 4682195 (1987-07-01), Yilmaz
Nakagawa et al., "Non-Latch-Up 1200V 75A Bipolar-Mode MOSFET with Large ASO", IEDM 1984, pp. 860-861.
Fuji Electric & Co., Ltd.
LaRoche Eugene R.
Shingleton Michael B.
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