Patent
1986-11-13
1987-07-14
Edlow, Martin H.
357 38, H01L 2978, H01L 2974
Patent
active
046806040
ABSTRACT:
There is a conductivity modulated MOS transistor comprising: a p-type region formed in the surface area of an n.sup.- -type layer formed on a p.sup.+ -type layer; an n.sup.+ -type region formed in the surface area of this p-type region to face the n.sup.- -type layer; and a gate electrode formed through a gate insulation layer over a surface region of the p-type region sandwiched between the n.sup.- -type layer and the n.sup.+ -type region. This MOS transistor further comprises a p.sup.+ -type region formed inside the p-type region, at least under the n.sup.+ -type region and having a higher impurity concentration than the p-type region.
REFERENCES:
patent: 4345265 (1982-08-01), Blanchard
patent: 4364073 (1982-12-01), Becke et al.
patent: 4503598 (1985-03-01), Vora et al.
patent: 4587713 (1986-05-01), Goodman et al.
Nakagawa Akio
Watanabe Kiminori
Edlow Martin H.
Kabushiki Kaisha Toshiba
Lamont John
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