Wave transmission lines and networks – Automatically controlled systems – Impedance matching
Reexamination Certificate
2001-12-12
2004-06-29
Lee, Benny (Department: 2817)
Wave transmission lines and networks
Automatically controlled systems
Impedance matching
C327S362000, C326S030000
Reexamination Certificate
active
06756858
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and, more particularly, to output drivers, and even more particularly to output impedance matching.
BACKGROUND OF THE INVENTION
As the number and complexity of computations and other functions performed by integrated circuit (IC) chips has increased, so has the speed required to effectively make these computations. For the clock rates at which modern integrated circuits operate, metal traces on the IC take on characteristics common to transmission lines. In order to maintain signal quality, it is necessary to minimize reflections and signal distortions which requires matching the output impedance of the signal source to that of the line.
The more functions the IC chip contains, the larger the number of circuit blocks which it typically has in order to communicate with other devices external to the IC. The circuit blocks that provide this interface function between the core functions of the IC and the outside world are referred to as input/output (I/O) PAD's. PAD blocks typically contain drivers for obtaining signals from other chip circuitry and driving them out of the chip and receivers for receiving signals from external devices and propagating those signals to other chip circuitry.
Contact between an integrated circuit and the outside world typically takes place through contact areas located near the outside edge of the chip. The denser chip circuitry is placed in locations removed from these contact areas, as stress produced during I/C contact formation is severe enough to cause damage to any circuitry that might be lying close to those contacts. In addition, damage produced in breaking the chips apart prior to packaging makes the peripherical chip area unsuitable for chip circuitry and thus available for chip contacts with their wider spacing.
The integrated circuit then will typically have its inner area devoted to active circuitry and its periphery area populated with chip contact areas, Relatively long conducting traces interconnect these two area. These traces then move the contact points to the active circuit areas of the integrated circuit from the inner areas of the chip to the outer areas where the contact to the outside world is created. This outer conducting layer then is often referred to as the redistribution metal layer, as it redistributes the output points from the input/output circuit blocks to points on the periphery of the IC. In common applications of the popular flip-chip technology, solder bumps bonded to the chip contact areas are bonded to traces in packages which are then mounted on printed circuit boards for interconnect to other integrated circuits and other devices.
Due to the fast clocking rates required in modem integrated circuits and the relatively long traces between chip circuitry and the chip contact areas, the resistance of these redistribution traces becomes significant. Of significance also are the differences between the various redistribution traces. As such, one chip contact area presents a different output impedance than does another. Such mismatches can degrade the speed at which a chip can reliably function. Minimizing these mismatches is a design objective, but one that often falls short. Processing variations add a further complicating variable which cannot be completely designed around. Thus, there is a need for a means to more effectively match the output impedance of integrated circuit I/O PAD's to the impedance of the lines which those input/output devices are driving.
SUMMARY OF THE INVENTION
Representative embodiments of a method for matching output impedance of a driver to a load impedance are disclosed. An external impedance is attached between an external contact and a first source potential, wherein the load impedance includes the external impedance plus impedance of interconnections between an output terminal of the driver and the external impedance. An adjustable impedance, which can be field effect transistors which can be turned on separately and in combination to change the value of the adjustable impedance and which can be located on an integrated circuit, are connected between a second source potential and the output terminal of the driver. A reference potential, wherein the reference potential has a value half-way between the first source potential and the second source potential is obtained. And a load matching impedance is obtained by changing the adjustable impedance until the absolute value of the difference between the voltage of the output terminal of the driver and the reference potential is less than a preselected value.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5459440 (1995-10-01), Claridge et al.
patent: 6486612 (2002-11-01), Fujimura et al.
patent: 6545522 (2003-04-01), Mughal et al.
Hayt et al., Engineering Circuit Analysis, 1978, McGraw-Hill Book Company, 3rd Edition, p. 68.
Gonzalez Jason
Welch M. Jason
Agilent Technologie,s Inc.
Jones Stephen E.
Lee Benny
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