Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2002-02-07
2003-06-24
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C257S737000, C361S767000, C361S783000
Reexamination Certificate
active
06583365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a substrate for BGA packaging structures and, more particularly, the invention relates to a conductive pad layout of the substrate used in BGA packaging structure.
2. Description of the Related Art
As high-density integrated circuit (IC) devices operate faster (order of MHz) and necessitate an increasing number of input/output (I/O) connections, higher performances of semiconductor packaging structures are required. In this context, traditional packaging structures such as Quad Flat Packages (QFP) or Pin-Grid Array (PGA) packages have reached their bottleneck. For illustration, QFP and PGA packaging structures usually provide a number of connection pins that vary within a limit of about 100 to 200, which is insufficient with respect to presently developed technology.
It is common for presently constructed personal computers to include 64-bits microprocessors. The core logic circuit of the personal computer has to be connected to the microprocessor and other devices including dynamic random access memory (DRAM) as principal memory of the system, and static random access memory (SRAM) as fast access memory. Additionally, the 64-bits microprocessor has to be connected to a 64-bits bus. As a result, if the core logic circuit is fabricated from a single IC chip, each data bus has to be corresponded to each address bus, which typically results in a number of connection pins amounting to 200. When other control signals are further included, this number easily exceeds 300 of connection pins.
Ball Grid Array (BGA) packaging structures offer many advantages that can fulfill the requirements of presently developed technology. BGA packaging structures provide a high number of I/O connections while enabling a size reduction of the packaging structure. Furthermore, by having short signal paths, BGA packaging structures generate reduced electrical inductance and reduced ground bounce.
BGA packaging structures are typically fabricated from a printed circuit substrate onto which a chip is attached and electrically connected. After the chip is mounted onto the circuit substrate, bonding wires are formed to connect the contact pads of the chip to the circuit substrate. An encapsulant material then is molded onto the chip, the bonding wires, and the circuit substrate, and via a reflow process, solder balls are formed on the bottom surface of the circuit substrate.
Referring to
FIG. 1
, a schematic view illustrates a conductive pad layout of conventional BGA packaging structures. In
FIG. 1
, a substrate
100
has front trace surface I on which is mounted a chip
120
, and a bottom trace surface II where the BGA packaging structure is connected to external devices. Both top trace surface I and bottom trace surface II are shown in juxtaposition way in
FIG. 1. A
plurality of contact pads (
111
,
112
,
113
) are defined in a contact pad zone
110
on the top trace surface I. The contact pad zone
110
is located at one side of the chip
120
.
A plurality of bonding wires (
131
,
132
,
133
) connect the chip
120
to the contact pads (
111
,
112
,
113
). The contact pads (
111
,
112
,
113
) connect to a plurality of vias (
151
,
152
,
153
) connected to corresponding ball pads (
141
,
142
,
143
).
Because the bonding wires (
131
,
132
,
133
) have the same length and are relatively long, crosstalk is conventionally generated between the bonding wires. Undesirable interference is also generated between the traces connecting vias (
151
,
152
,
153
) to the ball pads (
141
,
142
,
143
). As a result, signal transmission from the chip
120
through the BGA packaging structure may be negatively affected.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a conductive pad layout for BGA packaging structures that can reduce negative interference with respect to the contact pads that transmit critical signals.
To accomplish the above and other objectives, a conductive pad layout of the invention is implemented on a substrate for BGA packaging structures. The substrate has a top trace surface on which is mounted a chip, and an opposite bottom trace surface. A first contact pad and a second contact pad are defined on the top trace surface, wherein the second contact pad is closer to the chip than the first contact pad. The second contact pad transmits a critical signal of the BGA packaging structure. An anti-interference contact pad connected to a reference voltage is further defined adjacent to the second contact pad. First, second, and third bonding wires respectively connect the first, second, and anti-interference contact pads to the chip. The second and third bonding wires are shorter than the first bonding wire. With a shorter bonding wire and an adjacent reference contact pad, a critical signal is transmitted through the second bonding wire and the second contact pad with reduced interference. A less critical signal can be transmitted through the first bonding wire and the first contact pad. A first ball pad and a first via connected to the first ball pad are defined on the bottom trace surface. A second ball pad and a second via connected to the second ball pad are defined on the bottom trace surface. A dummy ball pad is further defined adjacent to the second ball pad. The first via connects the first contact pad via a first conductor member and the second via connects the second contact pad via a second conductor member. The dummy ball pad is defined as a reference connection of the substrate and does not connect any vias to reduce interference.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5343074 (1994-08-01), Higgins et al.
patent: 5599747 (1997-02-01), Bhatt et al.
patent: 5895967 (1999-04-01), Stearns et al.
patent: 6181005 (2001-01-01), Arimoto
patent: 6242814 (2001-06-01), Bassett
patent: 6414386 (2002-07-01), Beaulieu et al.
patent: 6433441 (2002-08-01), Niwa et al.
Norris Jeremy
Paladini Albert W.
Via Technologies Inc.
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