Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2002-07-26
2004-08-17
Zarroli, Michael C. (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C257S698000
Reexamination Certificate
active
06776622
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor structure and process, and more particularly to a conductive contact structure and a process thereof, which can reduce the resistance of the contact structure.
BACKGROUND OF THE INVENTION
Recently, along with progressive micro-sizing of semiconductor devices, wirings are getting more and more multi-layered when manufacturing semiconductor devices. As a result, steps in the manufacturing process of contact plugs or via plugs (generically called “contact plugs” hereinafter) are increasing, and manufacturing process of semiconductor devices are getting more and more complex.
A connection between a conductive region of an impurity diffused layer in a semiconductor substrate and an upper level wiring layer through a contact plug formed in an interlayer insulating film is one of the important fabrication techniques in a semiconductor device. As the degree of the integration density of integrated circuit device increases, contact openings for the contact plugs formed in the insulating layer are required to have a small opening size to ensure a high density device. In order to increase alignment margins between contact openings and overlying conductors, it is necessary that the critical dimension of the contact openings be reduced.
As decreases of critical dimensions of the contact openings continue, alignment tolerance of the photolithography process for fabricating the contact openings are relatively reduced. Therefore, higher precise control is required to prevent yield losses caused by misalignment errors, but this increased precision results in more manufacturing difficulty. It is necessary to develop a new advanced process having high alignment tolerance even under a lowered critical dimension.
Moreover, in the condition of minimizing critical dimension and the raising of wiring layers, the aspect ratio of the contact openings is increased, and this makes for more difficulty in filling the contact opening with conductive material. In the resulting contact plugs, voids are inevitably formed so that the resistance of the contact plugs is increased, and even a current short is created therein. Hence, operation speed of the devices is undeniably decreased, or failure-prone devices are unavoidably produced. Furthermore, the contact openings are traditionally filled with polysilicon to form contact plugs. Although the ohmic resistance in the bottom of the contact plane can be reduced, unfortunately, a native silicon oxide layer is naturally formed. In order to remove the native silicon oxide layer, a wet cleaning process is employed so that the neighboring silicon-based dielectric layer is damaged, and thus modifies the original size of the contact openings.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a conductive contact structure and process that decreases the aspect ratio of the contact openings and prevents formation of the voids in the contact plugs.
It is another object of the present invention to provide a conductive contact structure and process that can reduce the resistance of the contact structure and increase the operation speed of devices by utilizing the metal pad layer.
It is yet a further object of the present invention to provide a conductive contact structure and process that uses a metal pad layer without a native silicon oxide layer. The size of the contact openings above the metal pad will not be changed since there is no native silicon oxide layer is required to be removed.
In one aspect, the present invention provides a method of fabricating a conductive contact structure for electrically connecting to a source/drain region in a semiconductor substrate having a first dielectric layer thereon covering the source/drain region. The method comprises the following steps. A pad opening and a bottom opening are formed in the first dielectric layer. The pad opening is larger than and located upon the bottom openings to expose the source/drain region. The bottom opening and pad opening are filled with a polysilicon layer and a first metal layer, respectively. A second dielectric layer is formed on the first dielectric layer, and a top opening is formed therein. The top opening substantially shifting away from the bottom opening is smaller than and located upon the pad opening to expose the metal layer. The top opening is then filled with a second metal layer.
In another aspect, the present invention provides a conductive contact structure in a dielectric layer located on a semiconductor substrate to electrically connect to a source/drain region in the semiconductor substrate. The conductive contact structure comprises a bottom plug, a metal pad layer and a top plug. The bottom plug is disposed on and electrically connected to the source/drain region. The metal pad layer having a shape of bar is larger than the bottom plug. One end of the metal pad layer is disposed on and electrically connected to the bottom plug. The top plug is disposed on and electrically connected to the metal pad layer. The top plug has a location substantially shifted away from the bottom plug.
REFERENCES:
patent: 5838049 (1998-11-01), Nicholls et al.
patent: 6133628 (2000-10-01), Dawson
patent: 6522013 (2003-02-01), Chen et al.
patent: 2002/0163057 (2002-11-01), Bulovic et al.
patent: 2002/0163072 (2002-11-01), Gupta et al.
patent: 2002/0195638 (2002-12-01), Fechner et al.
patent: 2003/0015732 (2003-01-01), Park
Chuang Yueh-Cheng
Sheu Bor-Ru
Yang Shih-Hsien
Dickinson Wright PLLC
Winbond Electronics Corporation
Zarroli Michael C.
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