Conductive bumps with non-conductive juxtaposed sidewalls

Details Conductive bumps with non-conductive juxtaposed sidewalls Conductive bumps with non-conductive juxtaposed sidewalls

2006-12-26

2006-12-26

Smith, Zandra V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S734000, C257S748000

Reexamination Certificate

active

07154176

ABSTRACT:
A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.

REFERENCES:
patent: 6333555 (2001-12-01), Farnworth et al.
patent: 6767818 (2004-07-01), Chang et al.
patent: 2003/0183933 (2003-10-01), Kobayashi
patent: 2004/0219715 (2004-11-01), Kwon et al.

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