Conditioning of semiconductor wafers for uniform and repeatable

Details Conditioning of semiconductor wafers for uniform and repeatable Conditioning of semiconductor wafers for uniform and repeatable

1992-03-03

1994-03-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437241, H01L 2131

Patent

active

052963853

ABSTRACT:
Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow. This is due to the oxidation resistance and also etch resistance of silicon nitride. The backside structures disclosed prevent emissivity variations/drift during RTP and other device fabrication steps throughout an integrated flow.

REFERENCES:
patent: 4662956 (1987-05-01), Roth et al.
patent: 4687682 (1987-08-01), Koze
patent: 4956538 (1990-09-01), Moslehi

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