Conditional wait state generator circuit

Details Conditional wait state generator circuit Conditional wait state generator circuit

1995-12-07

1997-01-28

Heckler, Thomas M.

G06F 112

Patent

active

055985564

ABSTRACT:
A conditional wait state generator is interposed into the timing circuitry of a processor. The conditional wait state generator provides for analysis of a selected cycle type and for selection of the latency or number of wait states that is imposed during processor execution for that selected cycle type. In accordance with another aspect of the conditional wait state generator, a method of analyzing processor performance under specific operating conditions involves selection of a particular cycle type for testing and selection of a number of wait states that is imposed on processor operations for the selected cycle type and not for other cycle types. A conditional wait state generator is interposed into the timing circuitry of a processor and thereby imposes the selected conditions on the processor for analysis.

REFERENCES:
patent: 5151986 (1992-09-01), Langan et al.
patent: 5155812 (1992-10-01), Ehlig et al.
patent: 5201036 (1993-04-01), Yoshimatsu
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5448744 (1995-09-01), Eifert et al.
patent: 5452434 (1995-09-01), MacDonald

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