Conditional selection method for reducing power consumption in a

Details Conditional selection method for reducing power consumption in a Conditional selection method for reducing power consumption in a

1995-04-24

1997-12-09

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364491, G06F 1750

Patent

active

056966920

ABSTRACT:
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.

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