Condition code graph analysis for simulating a CPU processor

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3642323, 3642282, 3642321, 36492781, 3649338, G06F 900

Patent

active

049511955

ABSTRACT:
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application's instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction. Fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.

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