Condensed memory matrix

Details Condensed memory matrix Condensed memory matrix

2001-08-28

2003-09-16

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S106000, C438S110000, C438S460000, C438S712000

Reexamination Certificate

active

06620706

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains to wafer-scale integration (WSI) and, more particularly, to memory devices. It is specifically directed to a condensed memory matrix (CMM) having application to memory modules, memory cards, hard drives and the like.
2. State of the Art
Wafer-scale integration (WSI) refers generally to a method for maintaining functionally defined and independently testable “chips” (or dies) on a wafer. WSI has always been understood as a method of fabrication rather than a size of fabrication. Currently, while wafers are routinely constructed as discs up to nine (9) inches, more typically, wafers are produced being seven (7) inches in diameter, although the wafer size may vary as manufacturing capabilities vary. Conventionally, selected “good” chips are interconnected through wiring deposited on the wafer, rather than dicing the wafer and interconnecting individual chips by means of single chip packaging or other expedients. Portions of the disc, carrying a requisite number of dies, may be cut from the wafer for use in the construction of a device. The primary goal of WSI has been to increase system density beyond that achievable by maximizing chip size within an ordinary packaging environment. It is also generally understood that increasing density improves system performance and decreases system cost.
To realize increased density, good chip yield on the wafer must be very high. Otherwise, dilution of good chips with bad chips on the wafer will work against density gain. All of the chips on a wafer must ordinarily be fabricated from the same process for the wafer to be competitive, on either an economic or performance basis, with independently produced single chips. This is understood as meaning that all chips on a wafer must be of the same type (no mixing of DRAM, SRAM, Logic, EPROM, etc. on the same wafer). Wafers with only DRAM chips, especially DRAM chips of small size, find practical application in the construction of a memory.
U.S. Pat. No. 5,214,657 discloses a method for utilizing the good portions of an otherwise defective WSI wafer. Specifically, circuitry is provided to enable dicing of the wafer to salvage discrete memory sections should the wafer as a whole fail testing. Fuses in the wiring laid down on the wafer may selectively be blown to isolate defective dies from the circuits interconnecting the good dies.
Hybrid WSI (HWSI) has been suggested to avoid some of the practical limitations of WSI. HWSI involves mounting tested good chips of any type on a tested good wafer. The wafer provides passive chip interconnections, power distribution and intermediate cooling. The HWSI approach foregoes the economical benefits of conventional WSI and has the disadvantage of making cooling more difficult since the glue required to bond the chips to the wafer causes an additional temperature drop in the cooling path.
There remains a need in the art for further refinements in WSI technology whereby a wafer or a portion of a wafer may be connected to a substrate material, such as a substrate circuit board (SCB). Such a construction would increase system density in a memory device and would provide practical portability for such devices at low cost.
SUMMARY OF THE INVENTION
This invention may be viewed as an improvement in the fabrication of an electronic memory device including a plurality of dies (typically DRAM dies), carried by a wafer and connected through attachment bumps in circuit with wires carried by a substrate. In general, the improvement of the present invention comprises: providing a wafer with a first array of attachment bumps arranged in a first pattern; providing a substrate with a second array of attachment bumps arranged in a second pattern, the second pattern being the approximate mirror image of the first pattern; juxtaposing the first and second arrays of attachment bumps in mutually conductive relationship; and bonding the wafer to the substrate with a dielectric adhesive material. The present invention further includes the bonding of a heat dissipation device to the wafer using a thermally conductive adhesive material.
According to one embodiment of the invention, a condensed memory matrix (CMM) is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of chips (e.g., DRAM chips) and physically bonding the juxtaposed surfaces of the substrate and the wafer using a curable dielectric resin. The attachment bumps of the substrate need not be identical to, but must be complementary with (e.g., bondable to), the attachment bumps of the wafer. An array of heat fins is bonded to the inactive surface of the wafer using a thermally conductive curable resin. The materials and techniques useful for the fabrication of integrated circuit (IC) devices generally are acceptable for the fabrication of the condensed memory matrices of this invention. Dies of conventional dimension and properties are currently of greatest interest.
This invention provides for increased memory in the space available in modules or cards. It also offers increased storage capacity for hard drive units and for thinner package capability generally. The close proximity of dies in the memory matrix of this invention provides for increased operating speed to the devices incorporating portions of the matrix.
Physically, the condensed memory matrix structures of this invention comprise a conventional substrate, e.g., of silicone, ceramic, poly PCB or flex PCB material. A pattern or array of circuit connection structures, such as gold ball bumps, lead solder bumps or curable types (by air or heat) of attachment bumps, is carried on a first or “active” surface of the substrate in conventional fashion. A layer of low stress dielectric material, preferably a cured resin with adhesive properties, fills the interstices between the circuit connection structures. A wafer with a plurality of dies is mounted against the dielectric layer. A first or “active” surface of the wafer carries die connection structures, such as bumps, juxtaposed against and in conductive relationship as by fusing through a reflow type or curing process, with corresponding circuit connection structures carried by the substrate. The dielectric layer also fills the interstices between the die connection structures. A thermally conductive layer, such as an epoxy resin, bonds a heat dissipation device, such as an array of suitable type heat fins, to a second surface of the wafer opposite the first surface (carrying the die connection structures).
A novel, condensed memory matrix of this invention is fabricated by connecting a conventional wafer, a conventional substrate and a conventional heat dissipation device through, generally, the following sequence of steps:
1. Provide solder bumps for all appropriate bonding pads on a wafer.
2. Provide solder bumps at all appropriate locations on a substrate circuit board (SCB).
3. Dispense a nonconductive, low stress adhesive coating (such as an epoxy-based liquid polymeric adhesive) onto all appropriate locations on the SCB.
4. Align the wafer using conventional flip-chip bonding technology, with respect to the SCB such that the respective bumps of each are in approximate registration; e.g., a wafer may be positioned above an SCB with each bump bonded to the wafer's bonding pad located directly above a corresponding solder bump carried by the SCB.
5. Press the bumps of the wafer against those of the SCB, as by lowering the wafer onto the SCB with their respective bumps juxtaposed to each other. This step should preferably be conducted before the adhesive applied in step 3 is fully cured.
6. Allow the adhesive to cure. The solder bumps are then reflowed in conjunction with the epoxy through appropriate, well-known conventional processes, thereby fusing juxtaposed bumps together. The dies carried by the wafer, and thus the wafer, are thereby mechanically connected to the SCB.
7. Apply a thermally conductive layer, typically an uncured epoxy-based material, across the noncircuit

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