Boots – shoes – and leggings
Patent
1992-05-15
1996-06-11
Black, Thomas G.
Boots, shoes, and leggings
395650, 364489, G06F 1730
Patent
active
055265170
ABSTRACT:
An Electronic Computer Aided Design System provides for concurrent operation of a plurality of design tools which share a common design dataset. Changes made by one program to the design dataset are immediately updated and are automatically reflected in the displayed outputs of the other design tools. A tool manager program allows rule-based automation of the entire system.
REFERENCES:
patent: T940008 (1975-11-01), Oden
patent: T940020 (1975-11-01), Brechling et al.
patent: 4353117 (1982-10-01), Spellmann
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4635208 (1987-01-01), Coleby et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4697241 (1987-09-01), Lavi
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4789944 (1988-12-01), Wada et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4813013 (1989-03-01), Dunn
patent: 4827427 (1989-05-01), Hyduke
patent: 4831543 (1989-05-01), Mastellone
patent: 4833619 (1989-05-01), Shimizu et al.
patent: 4890238 (1989-12-01), Klein et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4965741 (1990-10-01), Winchell et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5034899 (1991-07-01), Schult
patent: 5084824 (1992-01-01), Lam et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5164908 (1992-11-01), Igarashi
"Quality Of Designs From An Automatic Logic Generator (ALERT)", by Friedman et al., IEEE Design Automation Conference, 1970, pp. 71-80.
"Switch-Level Delay Models For Digital MOS VLSI", by Ousterhout, IEEE 21st Design Automation Conference, 1984, pp. 542-548.
"Tango-Schematic Capture Software", PERX Catalog, pp. 18 & 19.
"Methods Used in an Automatic Logic Design Generator (ALERT)", by Friedman et al., IEEE Transactions On Computers, vol. C18, No. 7, Jul. 1969, pp. 593-614.
"An Efficient Heuristic Procedure for Partitioning Graphs", by Kernighan et al., The Bell System Technical Journal, Feb. 1970, pp. 291-306.
"Design Automation", by Russo, Computer, May/Jun. 1972, pp. 19-22.
"Computer Aided Design", by Lynn, Computer, May/Jun. 1972, pp. 36-45.
"Recent Developments in Design Automation", by Breuer, Computer, May/Jun. 1972, pp. 23-35.
"LINDA: A Local Interactive Design Aid For Computer-Aided General-Purpose Artwork Production", by Briggs, GEC Journal of Science & Technology, vol. 43, No. 2, 1976.
"An Engineering System for Designer, Manager and Manufacturer", by Smith et al., Telesis, vol. 4, No. 9, Dec. 1976, pp. 268-273.
"Computer Graphics In Power Plant Design", by Strong et al., IEEE Power Engineering Society, Jul. 1978.
"An Automated System to Support Design Analysis", By Willis, 12th Annual Asilomar Conference on Circuits, Systems & Computers, IEEE, Nov. 1978. pp. 646-650.
"Computer-Aided Partitioning of Behavioral Hardware Descriptions", by McFarland, 20th Design Automation Conference, IEEE, 1983, pp. 472-478.
"Definite Clause Translation Grammars", by Abramson, University of British Columbia, IEEE, 1984, pp. 233-240.
"VERIFY: A Program for Proving Correctness of Digital Hardware Designs", by Barrow, Artificial Intelligence 24, 1984, pp. 437-483.
"Automated Generation of Digital System Schematic Diagrmas", by Arya et al., 22nd Design Automation Conference, IEEE, 1985, pp. 388-395.
"Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions", by McFarland, 23rd Design Automation Conference, IEEE, 1986, pp. 474-480.
"Partitioning Before Logic Synthesis", by Camposano et al., IBM Thomas J. Watson Research Center, IEEE, 1987, pp. 324-326.
"Partitioning and Placement Technique for CMOS Gate Arrays", by Odawara et al., IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 3, May 1987, pp. 355-363.
"Partitioning a Design in Structural Synthesis", by Camposano et al., IBM Watson Research Center, IEEE, 1987, pp. 564-566.
"The System Architect's Workbench", by Thomas et al., 1988 DAC Draft Submission, Nov. 1987.
"Formal Verification of Digital Circuits Using Hybrid Simulation", by Srinivas et al., IEEE Circuits and Devices Magazine, Jan. 1988, pp. 19-26.
"Tektronix Design Automation Products", 1988. pp. 83-90.
"Formal Verification of the Sobel Image Processing Chip", by Narendran et al., 25th ACM/IEEE Design Automation Conference, 1988, pp. 211-217.
"Chip Simulation Is All A Matter of Image", by Thacker et al., ESD: The Electronic System Design Magazine, Nov. 1988, pp. 65-70.
"Area-Time Model for Synthesis of Non-Pipelined Designs", by Jain et al., CH2657-5 1988 IEEE, pp. 48-51.
"CAD For System Design: Is It Practical?", IEEE Design & Test of Computers, Apr. 1989, pp. 46-55.
"Acrhitectural Partitioning for System Level Design", by Lagnese et al., 26th ACM/IEEE Design Automation Conference, 1989, pp. 62-67.
"Here's Software To Speed Vector Creation", by Beaverton, Electronics, May 1989, pp. 48-52.
"Here's An Easy Way To Test ASICs", by McLeod, Electronics, May 1989, pp. 116-117.
"Experience with the ADAM Synthesis System", by Jain et al., 26th ACM/IEEE Design Automation Conference , 1989, pp. 56-61.
"Chippe: A System for Constraint Driven Behavioral Synthesis", by Brewer et al., IEEE Transactions on Computer-Aided Design, vol. 9, No. 7, Jul. 1990, pp. 681-695.
"BAD: Behavioral Area-Delay Predictor", by Kucukcakar et al., CEng Technical Report 90-31, Nov. 1990.
"HYPER-LP: A System for Power Minimization Using Architectural Transformations", by Chandrakasan et al., IEEE, 1992, pp. 300-303.
Eirikkson Asgeir Th.
Jones Edwin
Kong Soon
Black Thomas G.
LSI Logic Corporation
Wang Peter Y.
LandOfFree
Concurrently operating design tools in an electronic computer ai does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Concurrently operating design tools in an electronic computer ai, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Concurrently operating design tools in an electronic computer ai will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-362022