Concurrent task and instruction processor and method

Details Concurrent task and instruction processor and method Concurrent task and instruction processor and method

1978-10-16

1980-10-21

Malzahn, David H.

Boots, shoes, and leggings

G06F 918

Patent

active

042297907

ABSTRACT:
A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and instruction processing is carried on concurrently through the use of a snapshot taken of the next process status words (PSWs) to be serviced for each active task, the pointers for which are stored in task first in-first out buffers (task FIFOs). The PSWs, along with their parent task status words (TSWs), are placed into the control pipeline one at a time and serviced, after which each PSW pointer is placed back in the task FIFO from where it was taken. After all process status words of the snapshot have been entered into the control pipeline, a new snapshot is taken and the PSWs processed in the same manner. Instruction execution is carried out as the TSW/PSW pair proceeds through the control pipeline, during which time the required data operations are carried out by pulling operands from a memory unit, as required for execution of that particular instruction, and causing the same to be sent to the function units after which the results are placed in the memory unit. For interprocess data transfers, synchronization is accomplished through use of hardware implemented semaphores called a scoreboard. In addition, passage of data between processors and memories other than those associated, or local, memories, is through a memory switch.

REFERENCES:
patent: 3728692 (1973-04-01), Fennel, Jr.
patent: 3787673 (1974-01-01), Watson et al.

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