Concurrent simulation of host system at instruction level and in

Details Concurrent simulation of host system at instruction level and in Concurrent simulation of host system at instruction level and in

1994-05-16

1996-02-20

Kim, Ken S.

Boots, shoes, and leggings

395827, 364578, 364DIG1, 3642426, 3642423, 364802, G06F 1314

Patent

active

054936721

ABSTRACT:
A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.

REFERENCES:
patent: 4918594 (1990-04-01), Onizuka
patent: 5126966 (1992-06-01), Hafeman et al.
patent: 5134705 (1992-07-01), Smith et al.

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