Concurrent read/write architecture for a flash memory

Details Concurrent read/write architecture for a flash memory Concurrent read/write architecture for a flash memory

1998-01-23

1999-04-13

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518506, 36518511, G11C 1604

Patent

active

058944370

ABSTRACT:
A semiconductor device having an array of flash memory cells and for each column of cells, a global read bit line, a global write bit line, and a plurality of local bit lines, wherein the column of cells is divided into a plurality of subcolumns and each local bit line is electrically coupled to each of the cells in a subcolumn associated with the local bit line. The local bit line is coupled and decoupled to the global read bit line by a local read select transistor and is coupled and decoupled to the global write bit line by a local write select transistor. By coupling one local bit line for a column to the global read bit line and coupling another local bit line to the global write bit line, one cell can be written while another cell is read from, even though the cell being read and the cell being written are in the same column. A variation uses the two global bit lines as read lines or read/write lines instead of a global read bit line and a global write bit line for each column.

REFERENCES:
patent: 4970685 (1990-11-01), Koyanagi
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5448518 (1995-09-01), Jinbo
patent: 5682350 (1997-10-01), Lee et al.
patent: 5793666 (1998-08-01), Yamazaki

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