Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
2008-12-12
2011-12-13
Faherty, Corey S (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S010000
Reexamination Certificate
active
08078839
ABSTRACT:
An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.
REFERENCES:
patent: 4720780 (1988-01-01), Dolecek
patent: 5465368 (1995-11-01), Davidson et al.
patent: 5930522 (1999-07-01), Fant
Connolly Bove & Lodge & Hutz LLP
Faherty Corey S
Wave Semiconductor
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