Concurrent carrier and clock synchronization for data transmissi

Details Concurrent carrier and clock synchronization for data transmissi Concurrent carrier and clock synchronization for data transmissi

1980-08-05

1983-12-06

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 81, 375120, 329 50, H03L 706

Patent

active

044197594

ABSTRACT:
The present invention is directed to circuitry for achieving concurrent synchronization of carrier phase and clock timing in double-sideband, suppressed carrier transmissions systems. A phase-lock loop (PLL) is used in the respective carrier and clock recovery networks. The carrier recovery loop is similar to the conventional "Costas Loop". The PLLs are cross coupled in an interdependent recovery structure to enable a more effective clock and carrier regeneration.

REFERENCES:
patent: 3701948 (1972-10-01), McAuliffe
patent: 3984778 (1976-10-01), Bhopale
patent: 4085378 (1978-04-01), Ryan
patent: 4101844 (1978-07-01), Malone

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