Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-06-30
2004-05-11
Ngo, Ricky (Department: 2662)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S392000, C370S406000, C370S466000, C370S469000, C370S510000, C370S512000
Reexamination Certificate
active
06735197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communications, and, more particularly, efficiency in data communication circuits.
2. Description of the Related Art
A data communications network is the interconnection of two or more communicating entities (i.e., data sources and/or sinks) over one or more data links. A data communications network allows communication between multiple communicating entities over one or more data communications links. High bandwidth applications supported by these networks include streaming video, streaming audio, and large aggregations of voice traffic. In the future, these demands are certain to increase. To meet such demands, an increasingly popular alternative is the use of lightwave communications carried over fiber optic cables. The use of lightwave communications provides several benefits, including high bandwidth, ease of installation, and capacity for future growth.
The synchronous optical network (SONET) protocol is among those protocols designed to employ an optical infrastructure and is widely employed in voice and data communications networks. SONET is a physical transmission vehicle capable of transmission speeds in the multi-gigabit range, and is defined by a set of electrical as well as optical standards.
In some networks, network nodes store data which they use for proper operation. In SONET, data between adjacent nodes are transmitted in modules called STS's (synchronous transport signals). Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds). See Bellcore Generic Requirements document GR-253-CORE (Issue 2, December 1995) incorporated herein by reference. An STS-1 is a Synchronous Transport Signal-level 1 is the basic module in SONET and is defined as a specific sequence of 810 bytes (6480 bits) including overhead bytes and an envelope capacity for transporting payloads. In general, the higher-level signals, the STS-N signals, are lower-level modules that are multiplexed together and converted to an OC-N or STS-N signal. An STS-N frame is a sequence of N×810 bytes wherein N is a predetermined number. An STS-N is formed by byte-interleaving of STS-1 and STS-M modules, wherein M is less than N.
In some systems, such as certain ISDN and ATM systems, multiple STS-1 payloads are transported as super rate payloads. To accommodate such a payload an STS-Nc module is formed by linking N constituent STS-1s together in fixed phase alignment. The payload is then mapped into a single STS-Nc Synchronous Payload Envelope (SPE) for transport. Network equipment supporting the multiplexing, switching or transport of STS-Nc SPES treat an STS-Nc SPE as a single entity. When an STS-Nc SPE is treated as a single entity, concatenation indicators are present in the second through the Nth STS payload pointers which show that the STS-1s in the STS-Nc are linked together. The concatenation indicators do not, however, indicate when a concatenated STS-Nc is spread across multiple ASICs (Application Specific Integrated Circuit). Moreover, typically ASIC devices have limited pin availability compounding the problem.
It is desirable to have a system and method for detecting a concatenated STS-Nc that is spread across multiple ASICs.
SUMMARY OF THE INVENTION
Accordingly a system and method for detecting concatenation of payload data in a communication circuit, wherein the payload data is dispersed over a first integrated circuit and one or more subsequent integrated circuits, includes determining whether each of the one or more subsequent integrated circuits have all channels therein designated as concatenation slaves, and communicating the determination to the first integrated circuit, the determination indicating that the one or more subsequent integrated circuits are concatenation slaves. According to an embodiment, the method includes coupling the first integrated circuits to the one or more subsequent integrated circuits. The method further includes detecting concatenation on a first integrated circuit of the one or more integrated circuits, assigning one or more bi-directional ports coupled to the first integrated circuit as an input port, assigning each bi-directional port coupled to the one or more subsequent integrated circuits as an output port, and if any one integrated circuit among the subsequent integrated circuits includes a channel therein designated as a slave channel, providing an active high signal to the output port, the active high signal coupled to the input port of the first integrated circuit.
In one embodiment, the concatenation detection includes coupling the integrated circuits with a wire. The wire is further coupled to a pull up resistor to enable an active low signal and a tri stated signal. In another embodiment, the integrated circuits are disposed on an ASIC.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
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Duschatko Douglas E.
Hall Robert A.
Quibodeaux Lane Byron
Thurston Andrew J.
Campbell Stephenson Ascolese LLP
Cisco Technology Inc.
Ngo Ricky
Nguyen Alan V.
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