Computing system interface using common parallel bus and segment

Details Computing system interface using common parallel bus and segment Computing system interface using common parallel bus and segment

1971-08-31

1976-06-08

Springborn, Harvey E.

Communications: electrical

Digital comparator systems

G06F 900

Patent

active

039626849

ABSTRACT:
A computing system includes a central processor unit (CPU) integrated on a monolithic chip, in combination with a plurality of external memory units. The CPU includes a parallel arithmetic logic unit (ALU) and an internal random access memory interconnected on a common parallel bus with an instruction register. The random access memory defines the general purpose data registers, program and memory address registers, and a multilevel program address stack. Timing circuitry in the CPU enables utilization of either serial or random access external memory units. The timing control of the CPU enables a method of operation characterized by sequential transmission of low order address bits, WRITE data, high order address bits and READ data over a common external parallel bus that interconnects the CPU with the external memory.

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patent: 3629857 (1971-12-01), Faber
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