Computing device for nth degree functions

Details Computing device for nth degree functions Computing device for nth degree functions

1996-03-26

1997-07-01

Malzahn, David H.

Boots, shoes, and leggings

G06F 1711

Patent

active

056445180

ABSTRACT:
An nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present and which allows high-speed computing operations. The nth degree function computing device comprises two series operators 32 and 38 connected in series, with an adder 44 inserted between them, and with an adder 48 inserted between the output terminal of the second-stage series operator 38 and device output terminal 46. A constant 2a.sub.2 is sent from constant generator 50 to the first input terminal of an adder 34 of the first-stage series operator 32. A constant (a.sub.1 -a.sub.2) is sent from constant generator 52 to first input terminal of adder 44. A constant a.sub.0 is sent from constant generator 54 to the first input terminal of adder 48. With respect to variable x (integer), a clock circuit 56 sends (x+1) synchronized clock pulses CLK.sub.i and x clock pulses CLK.sub.k to registers 36 and 42 of first-stage and second-stage series operators 32 and 38, respectively.

REFERENCES:
patent: 3922536 (1975-11-01), Hampel et al.
patent: 3967100 (1976-06-01), Shimomura
patent: 3978326 (1976-08-01), Shimomura
patent: 5060181 (1991-10-01), Matsuoka
patent: 5235535 (1993-08-01), Nakayama
patent: 5377130 (1994-12-01), Frank et al.

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