Boots – shoes – and leggings
Patent
1994-03-14
1996-09-10
Oberley, Alvin E.
Boots, shoes, and leggings
395775, 364258, 364DIG1, G06F 100, G06F 300
Patent
active
055554342
ABSTRACT:
A computing device implements a functional programming in hardware and operates as a reduction processor. Programs to be evaluated are represented as a directional graph of closures, where each part of a program is represented by a closure. During execution, this directional graph of closures is gradually reduced according to the reduction rules of the declarative language used. The device has an active associative object storage having storage cells able to store and execute at least part of a computer program. The device has several ports that contain storage cells and which are able to exchange and compare data and programs through a unification of internal and external behaviors.
REFERENCES:
patent: 3253265 (1966-05-01), Lindquist
patent: 3413616 (1968-11-01), Lindquist
patent: 4075689 (1978-02-01), Berkling
patent: 4447875 (1984-05-01), Bolton et al.
patent: 4502118 (1985-02-01), Hagenmaier, Jr. et al.
patent: 4598361 (1986-07-01), Logsdon et al.
patent: 4616303 (1986-09-01), Logsdon et al.
patent: 4616315 (1986-10-01), Logsdon et al.
patent: 4654780 (1987-03-01), Logsdon et al.
patent: 4734848 (1988-03-01), Yamano et al.
patent: 4755974 (1988-07-01), Yamada et al.
patent: 5072422 (1991-12-01), Rachels
patent: 5173872 (1992-12-01), Crawford et al.
Patrick G. McKeown, Living With Computers, 1988, Chapter 3.
By M. Ercegovac et al., "Reduction Machines", High-level language computer architecture, 1989, Chapter 11, pp. 413-469.
"Pegasus--An ASIC Implementation of High Performance Prolog Processor" by Yokota, T. et al, EURO ASIC '90, pp. 156-159.
"An Associative Processor for Logic Programming Languages" by Naganuma, J., System Sciences, 1991 Annual Hawaii Int'l Conference pp. 229-236.
"A Tag Coprocessor for RISC Architectures" by Cheung, P. et al, IEEE Colloq. (1991) No. 163: RISC Architectures and Applications.
"Silicon Compilation of Algorithm Structures" by Gaillard, T. et al, EURO ASIC '90, pp. 480-484.
"Extending a Prolog Architecture for High Performance Numeric Computations" by Yung, R. et al, System Sciences, 1989 Annual Hawaii Int'l. Conference, vol. I pp. 393-402.
"Performance Evaluation of Integrated Prolog Processor IP.P" by Abe, S. et al, Artificial Intelligence for Industrial Applications, 1988, pp. 505-510 .
Carlstedt Elektronik AB
Oberley Alvin E.
Richey Michael T.
LandOfFree
Computing device employing a reduction processor and implementin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computing device employing a reduction processor and implementin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computing device employing a reduction processor and implementin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1328943