Computing carry-in bit to most significant bit carry save...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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10702992

ABSTRACT:
A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

REFERENCES:
patent: 4556948 (1985-12-01), Mercy
patent: 5303176 (1994-04-01), Hrusecky et al.
patent: 5805491 (1998-09-01), Bechade
patent: 5818747 (1998-10-01), Wong
patent: 6415311 (2002-07-01), Purcell et al.
patent: 6466960 (2002-10-01), Winters
patent: 6567835 (2003-05-01), Blomgren et al.
patent: 2003/0014459 (2003-01-01), Fletcher

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