Computer with main memory and cache memory for employing array d

Details Computer with main memory and cache memory for employing array d Computer with main memory and cache memory for employing array d

1991-06-14

1994-12-06

Robertson, David L.

Boots, shoes, and leggings

395425, 395375, 364DIG1, 3642624, 364255, 36424342, G06F 1202, G06F 1208

Patent

active

053718658

ABSTRACT:
A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.

REFERENCES:
patent: 4086629 (1978-04-01), Desyllas et al.
patent: 4095269 (1978-06-01), Kawabe et al.
patent: 4583165 (1986-04-01), Rosenfeld
patent: 4888679 (1989-12-01), Fossum et al.
patent: 4926323 (1990-05-01), Baror et al.
Journal of Parallel and Distributed Computing, "Strategies for Cache and Local Memory Management by Global Program Transformation", Oct. 5, 1988, No. 5, pp. 587-616.
Horikawa T. et al. "Performance Evaluation Of Cache Memory With A Prefetch Mechanism," Proceedings of IPSJ Annual Conference (Fall 1987), pp. 183-184.

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