Computer with instruction prefetch queue retreat unit

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Details

3642615, 3642631, 3642386, 3642624, G06F 938

Patent

active

049741543

ABSTRACT:
A computer comprises an instruction execution unit for running a first instruction loaded in an area classified by a first area recognition symbol of a storage for loading a plurality of instructions in a plurality of areas ordered by the area recognition symbols. An instruction analyzer (instruction decoding unit) is connected to said instruction execution unit for analyzing a second instruction loaded in an area classified by a second area recognition symbol. An instruction prefetch queue is connected between the instruction decoding unit and the main memory storage. A target prediction unit (branch target buffer) for predicting whether or not the second instruction is a branch instruction for running a fourth instruction loaded in an area classified by a fourth area recognition symbol is connected to the instruction prefetch queue, and an instruction prefetch queue retreat unit, wherein a part or all of the third instructions fetched in the instruction prefetch unit is stored temporarily when the target prediction unit predicts that the fourth instruction will be executed after instruction of the second instruction, is connected to the instruction prefetch queue and the instruction analyzer.

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patent: 4679141 (1987-07-01), Pomerene et al.
patent: 4691277 (1987-09-01), Kronstadt et al.
patent: 4714994 (1987-12-01), Oklobdzija et al.
patent: 4742451 (1988-05-01), Bruckert et al.
patent: 4758949 (1988-07-01), Wada et al.
patent: 4763245 (1988-08-01), Emma et al.

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