Patent
1996-12-18
1999-06-29
Lim, Krisna
395385, 395595, G06F 930
Patent
active
059180315
ABSTRACT:
A microarchitecture that accommodates divergent instruction sets having different data sizes and addressing modes utilizes a mechanism for translating a generic flow for an instruction into specific operations at run-time. These generic flows use a special class of micro-ops (uops), called "super-uops" (or "Suops)" which are translated into a variable number of regular (i.e., simple) uops. A first-level decoder translates macroinstructions into either simple micro-ops or one or more super-uops which represent one or more sequences of one or more simple uops. A second-level decoder is responsible for converting the super-uops into the appropriate micro-op sequence based upon a set of arguments associated with the super-uop and attributes of the macroinstruction.
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Kelm Andrew Paul
Morrison Michael J.
Zaidi Nazar A.
Zaveri Bharat N.
Intel Corporation
Lim Krisna
Vu Viet
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