Boots – shoes – and leggings
Patent
1985-07-03
1988-11-08
Eng, David Y.
Boots, shoes, and leggings
G06F 1516
Patent
active
047837349
DESCRIPTION:
BRIEF SUMMARY
The invention relates to microcomputers and particularly to microcomputers arranged to permit data transmission between processes.
BACKGROUND OF THE INVENTION
The present invention is a development of the microcomputer described in our European patent specification No. 0113516. That specification describes the microcomputer with a memory and processor arranged to execute a plurality of concurrent processes and to provide synchronised communication between concurrent processes on the same microcomputer or interconnected microcomputers. However, the device described in that specification was arranged to transmit messages which were each of one word length. After execution of each message instruction one word is transmitted and subsequent message instructions are required in order to cause further words to be transmitted. In the case of a 16 bit machine each message would be of 16 data bits.
OBJECTS OF THE PRESENT INVENTION
It is an object of the present invention to provide an improved microcomputer which permits variable length message transmission.
It is a further object of the present invention to provide an improved microcomputer which may transmit messages in multiples of standard bit length units.
It is a further object of the present invention to provide a microcomputer which may communicate in a network with other devices of different wordlength.
SUMMARY OF THE INVENTION
The invention provides a microcomputer comprising memory and a processor arranged to execute a plurality of concurrent processes, each in accordance with a program consisting of a plurality of instructions for sequential execution by the processor, each instruction designating a required function to be executed by the processor, said processor comprising (1) a plurality of registers and data transfer means for use in data transfers to and from said registers (2) means for receiving each instruction and loading into one of the processor registers a value associated with the instruction, and (3) control means for controlling said data transfer means and registers in response to each instruction received to cause the processor to operate in accordance with the instruction, wherein the microcomputer includes:
(a) scheduling means to enable the processor to share its processing time between a plurality of concurrent processes, said scheduling means comprising: collection awaiting execution by the processor current process execution, and
(b) communication means to permit message transmission from one process to another by use of one or more communication channels when both processes are at corresponding stages in their program sequences, an outputting process operating to output data and an inputting process operating to input data in response to message instructions, said communication means including: message unit of predetermined but length count of the number of mesaage units to be included in a message. instruction by an outputting process to indicate the address from which data is to be output, and instruction by an inputting process to indicate the address to which the data is to be input.
Preferably said predetermined bit length of each message unit is one byte. Preferably the microcomputer includes means for counting the number of bytes transmitted in a message to or from a process and providing a signal when all bytes in the message have been transmitted.
Preferably, means are provided to alter the address indicated by the source indicator means as the count of the number of bytes remaining to be transmitted decreases.
Preferably, means is provided to change the address indicated by the destination indicator means as the count of the number of bytes remaining to be transmitted changes.
Preferably, the communication means is arranged to permit data transmission between processes which are executed on the same microcomputer and said channel comprising a memory location.
Preferably, the processor has means for copying directly a number of bytes of data indicated as a result of execution of a message instruction, directly fr
REFERENCES:
patent: 4060849 (1977-11-01), Bienvenu et al.
patent: 4075691 (1978-02-01), Davis et al.
patent: 4084228 (1978-04-01), Dufond et al.
May Michael D.
Shepherd Roger M.
Eng David Y.
Inmos Limited
Manzo Edward D.
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