Computer system with PCI repeater between primary bus and second

Details Computer system with PCI repeater between primary bus and second Computer system with PCI repeater between primary bus and second

1996-12-23

1998-09-01

Ray, Gopal C.

395308, 395309, G06F 1300

Patent

active

058023240

ABSTRACT:
A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.

REFERENCES:
patent: 5596729 (1997-01-01), Lester et al.
patent: 5621900 (1997-04-01), Lane et al.
patent: 5664124 (1997-09-01), Katz et al.
patent: 5673399 (1997-09-01), Guthrie et al.
patent: 5673400 (1997-09-01), Kenny
Pico/Power.RTM., A Cirrus Logic Division; PT80C524 Preliminary Data Book; Version 0.7, Aug. 1995.

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