Computer system with means for regulating effective processing r

Details Computer system with means for regulating effective processing r Computer system with means for regulating effective processing r

1989-04-14

1991-08-20

Shaw, Gareth D.

Boots, shoes, and leggings

364270, 36424341, 3642405, G06F 13362

Patent

active

050419625

ABSTRACT:
A digital computer system having a local cache memory and a system bus also has a subsystem for regulating the effective processing rate of the central processor unit (CPU) of the computer system. A programmable counter/timer is programmed by data from the CPU to provide a periodic pulse of desired periodicity and pulse width for entry into a bus controller. The bus controller arbitrates use of the system bus, sending a request signal to the CPU requesting the CPU to relinquish use of the bus and it receives an acknowledgement signal from the CPU indicating its relinquishment of use of the bus. The local cache memory is flushed through the cache controller to prevent the CPU from using the local cache memory. This causes the CPU to be periodically active when using the system bus and periodically inactive when the system bus is relinquished, thereby establishing the effective processing rate of the CPU as set by the programmable counter/timer.

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