Boots – shoes – and leggings
Patent
1991-05-31
1992-11-03
Fleming, Michael R.
Boots, shoes, and leggings
395325, 364243, 3642434, 36424341, 364DIG1, 3642281, 3642397, 365 49, 36523001, 36523003, G06F 1200, G06F 1300
Patent
active
051612194
ABSTRACT:
A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.
REFERENCES:
patent: 3713107 (1973-01-01), Barsamian
patent: 3771137 (1973-11-01), Barner et al.
patent: 4051461 (1977-09-01), Hashimoto et al.
patent: 4071890 (1978-01-01), Pandeya
patent: 4075686 (1978-02-01), Calle et al.
patent: 4212057 (1980-07-01), Denlin et al.
patent: 4322795 (1982-03-01), Lange et al.
patent: 4355356 (1982-10-01), Bavousc et al.
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4395758 (1983-07-01), Helenius et al.
patent: 4399506 (1983-08-01), Evans et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4451884 (1984-05-01), Heath et al.
patent: 4484262 (1984-11-01), Sullivan et al.
patent: 4493051 (1985-01-01), Brezzo et al.
patent: 4509116 (1985-04-01), Lackey et al.
patent: 4521846 (1985-06-01), Scalzi et al.
patent: 4564900 (1986-01-01), Smitt
patent: 4654778 (1987-03-01), Chiesa et al.
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4677546 (1987-06-01), Freeman et al.
patent: 4700292 (1987-10-01), Campanini
patent: 4729094 (1988-03-01), Zolnowski et al.
patent: 4775955 (1988-10-01), Liu
patent: 4782439 (1988-11-01), Borkar et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4847750 (1989-07-01), Daniel
patent: 4870565 (1989-09-01), Yamamoto et al.
patent: 4912632 (1990-03-01), Gach et al.
patent: 4939636 (1990-07-01), Nakagawa et al.
Yen et al., "Shared Cache for Multiple-Stream Computer Systems", IEEE Trans. on Comp., vol. C-32, No. 1, Jan. 1983, pp. 38-47.
Smith; Alan J., "Cache Memories", ACM Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530.
Yen et al., "Data Coherence Problem in a Multicache System", IEEE Trans. on Comp., vol. C-34, No. 1, Jan. 1985, pp. 56-65.
IBM Technical Disclosure Bulletin, J. W. Kemp, D. P. Tuttle and M. A. Wieland, vol. 28, No. 9, Feb. 1986.
IBM Technical Disclosure Bulletin, J. T. O'Quin II, vol. 29, No. 4, Sep. 1986.
Nicholson James O.
O'Quin, II John T.
O'Quin, III John C.
Strietelmeier Frederick E.
Fleming Michael R.
International Business Machines - Corporation
O'Malley Paul W.
Ray Gopal C.
LandOfFree
Computer system with input/output cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer system with input/output cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system with input/output cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2056639