Boots – shoes – and leggings
Patent
1996-01-19
1998-05-19
Bowler, Alyssa H.
Boots, shoes, and leggings
395306, 395307, 395821, 395847, 395886, 364DIG1, G06F 314
Patent
active
057548757
ABSTRACT:
A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.
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Getzlaff Klaus Jorg
Hajdu Johann
Haller Wilhelm Ernst
Withelm Birgit
Bowler Alyssa H.
International Business Machines - Corporation
Nguyen Dzung C.
Samodovitz Arthur J.
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