Computer system with cascaded peripheral component interconnect

Details Computer system with cascaded peripheral component interconnect Computer system with cascaded peripheral component interconnect

1995-10-25

1997-05-20

Ray, Gopal C.

395308, G06F 1300, G06F 1338, G06F 1342

Patent

active

056320213

ABSTRACT:
A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secondary bus, the second bridge is configured to only act as master on the primary bus and as a target on the secondary bus. The determination of which data path is chosen is not made by the bridges and thus the bridges do not bias the direction of transmissions to one bus or to the other bus.

REFERENCES:
patent: 5360952 (1994-11-01), Brajczewski et al.
patent: 5533204 (1996-07-01), Tipley
patent: 5535340 (1996-07-01), Bell et al.
patent: 5542053 (1996-07-01), Bland et al.
patent: 5542055 (1996-07-01), Amini et al.
patent: 5542056 (1996-07-01), Jaffa et al.
patent: 5548730 (1996-08-01), Young et al.
patent: 5555383 (1996-09-01), Elazar et al.
patent: 5557758 (1996-09-01), Bland et al.

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