Patent
1995-02-13
1996-07-09
Elmore, Reba I.
395447, 39542111, 395405, G06F 1208
Patent
active
055353592
ABSTRACT:
A computer system is provided with a plurality of cache memories. Each cache memory stores data corresponding to part of main memory address space without overlapping with each other, thereby enabling capacity of the cache memory to be increased with ease. An address mask register is used to allocate the portion of main memory address space stored in each cache.
REFERENCES:
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 4574346 (1986-03-01), Hartung
patent: 4885680 (1989-12-01), Anthony et al.
patent: 4914577 (1990-04-01), Stewart et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 4996641 (1991-02-01), Talgam et al.
patent: 5008813 (1991-04-01), Crane et al.
patent: 5010475 (1991-04-01), Hazawa
patent: 5056041 (1991-10-01), Guttag et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5091850 (1992-02-01), Culley
patent: 5148536 (1992-09-01), Witek et al.
patent: 5157774 (1992-10-01), Culley
patent: 5163142 (1992-11-01), Mageau
Hata Masayuki
Nakagawa Hiromasa
Yamada Tatsuo
Elmore Reba I.
Mitsubishi Denki & Kabushiki Kaisha
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