Computer system with a semi-differential bus signaling scheme

Details Computer system with a semi-differential bus signaling scheme Computer system with a semi-differential bus signaling scheme

1997-09-26

2000-11-28

Chin, Stephen

Pulse or digital communications

Cable systems and components

375377, 375259, 375354, 327297, 327291, 327141, H04B 300, H04L 2300, H04L 2700, H03K 300

Patent

active

061544981

ABSTRACT:
A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

REFERENCES:
patent: 5864253 (1999-01-01), Katakura et al.
Gunning et al., "A CMOS Low-Voltage-Swing Transmission-Line Transceiver, " Proceedings of 1992 IEEE International Solid-State Circuits Conference, pp. 58-59 (1992).

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