Computer system with a memory access arbitrator

Details Computer system with a memory access arbitrator Computer system with a memory access arbitrator

1976-09-28

1978-06-20

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 918, G06F 1300

Patent

active

040965724

ABSTRACT:
A micro-computer system includes a memory device, a plurality of memory utilization devices such as processors, a bus connected between the memory device and the memory utilization devices for address information and data transfer therebetween, bus control lines, and an access arbitrator for preventing simultaneous accesses of memory utilization devices to the memory device. The bus control lines include two lines for transferring address transfer and write/read control information from one of the memory utilization devices to the memory device and one line for coupling an access acknowledge signal from the memory device to one of the memory utilization devices. The access arbitrator couples the access acknowledge signal to one of the memory utilization devices issuing an access request signal and disables another memory utilization device to issue the address transfer and read/write control information on the two bus control lines.

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patent: 3761879 (1973-09-01), Brandsma
patent: 3775754 (1973-11-01), Auspurg et al.
patent: 3787818 (1974-01-01), Arnold et al.
patent: 3810105 (1974-05-01), England
patent: 3921145 (1975-11-01), Emm et al.
patent: 3959775 (1976-05-01), Valassis et al.

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