Computer system which switches bus protocols and controls the wr

Details Computer system which switches bus protocols and controls the wr Computer system which switches bus protocols and controls the wr

1995-04-26

1997-04-01

Kulik, Paul V.

395417, G06F 906

Patent

active

056175531

ABSTRACT:
An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer includes an address buffer translator which translates a virtual address to a physical address and produces a bus protocol specifying signal. A bus interface changes bus protocols in accordance with the bus protocol specifying signal in order to permit a transfer of a physical address and data on the bus. In another embodiment, when the data in a cache memory is changed, a dirty bit for the cache memory is set but a corresponding dirty bit in the address translation buffer is not changed until a copy-back operation from the cache memory to a main memory occurs. The dirty page bit of the address translation buffer is changed utilizing software.

REFERENCES:
patent: 4933835 (1990-06-01), Sachs et al.
patent: 5347636 (1994-09-01), Ooi et al.

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