Computer system using multidimensional addressing between multip

Details Computer system using multidimensional addressing between multip Computer system using multidimensional addressing between multip

1990-07-13

1996-12-17

Lee, Thomas C.

Boots, shoes, and leggings

395507, 364133, 3642319, 3642551, 364228, 364DIG1, G05B 1500

Patent

active

055862560

ABSTRACT:
A computer system includes sixteen data processors each connected to a communication bus. The communication bus comprises a data bus for carrying data, and an address bus for carrying associated labelling information uniquely identifying the data. Each processor includes read and write detectors connected to the address bus for detecting labelling information of data required by, or presently stored in, respectively, the data processor. A bulk memory having similar read and write detectors is connected to the communication bus. An address generator supplies labelling addresses to the address bus. For each address, one processor or the bulk memory supplies the corresponding data to the data bus, and other processors and/or the bulk memory requiring the data read the data from the data bus. Data is transferred between processors and/or the bulk memory in this way. The address bus and the read and write decoders are configured for multi-dimensional addressing.

REFERENCES:
patent: 3851313 (1974-11-01), Chang
patent: 4045781 (1977-08-01), Levy et al.
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 4107780 (1978-08-01), Grimsdale et al.
patent: 4163280 (1979-07-01), Mori et al.
patent: 4210879 (1980-01-01), Pandeya
patent: 4222102 (1980-09-01), Jansen et al.
patent: 4231088 (1980-10-01), Hammer et al.
patent: 4315312 (1982-02-01), Schmidt
patent: 4344130 (1982-08-01), Fung et al.
patent: 4459664 (1984-07-01), Pottier et al.
patent: 4608629 (1986-08-01), Nagel
patent: 4766534 (1988-08-01), De Benedictis
patent: 4803617 (1989-02-01), Berarducci
patent: 4809159 (1989-02-01), Sowa
patent: 4855903 (1989-08-01), Carleton et al.
patent: 4954951 (1990-09-01), Hyatt
patent: 4959776 (1990-09-01), Deerfield et al.
patent: 5086498 (1992-02-01), Tanaka et al.
patent: 5293481 (1994-03-01), Mita et al.
1986 Proceedings Fall Joint Computer Conference, "Autonomous Decentralized Software Structure and Its Application", Kinji Mori et al, pp. 1056-1063.
"Nedips: A Non-von Neumann High-Speed Computer", Nobuyasu Ito et al, Jul. 1985, pp. 83-90.
"Multiprocessor scheme with application to macro-dataflow," Abdulkarim Ayyad et al, Jun. 1987, pp. 255-263.
Technology Updates, "Software machine model blazes trail for parallel processing", Tom Williams, Oct. 1, 1988, pp. 20, 22, 24, 26.
"Topological Comparison of Static Multiprocessing Networks," Ran Ginosar et al, Technion-Israel Institute of Technology, May 23, 1989, pp. 1-4.

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