Multiplex communications – Wide area network – Packet switching
Patent
1996-05-24
1999-02-16
Luu, Le Hien
Multiplex communications
Wide area network
Packet switching
39518201, 39518307, 39520069, 370287, G06F 1300
Patent
active
058729046
ABSTRACT:
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log.sub.b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log.sub.b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
REFERENCES:
patent: 3290446 (1966-12-01), Ceonzo
patent: 3317676 (1967-05-01), Ekbergh et al.
patent: 3491211 (1970-01-01), Bininda et al.
patent: 3581286 (1971-05-01), Beausolell
patent: 3582560 (1971-06-01), Banks
patent: 3693155 (1972-09-01), Crafton et al.
patent: 3963872 (1976-06-01), Hagstrom et al.
patent: 4022982 (1977-05-01), Hemdal
patent: 4038638 (1977-07-01), Hwang
patent: 4074072 (1978-02-01), Christensen et al.
patent: 4075693 (1978-02-01), Fox et al.
patent: 4081612 (1978-03-01), Hafner
patent: 4146749 (1979-03-01), Pepping et al.
patent: 4173713 (1979-11-01), Giesken
patent: 4177514 (1979-12-01), Rupp
patent: 4201889 (1980-05-01), Lawrence et al.
patent: 4201891 (1980-05-01), Lawrence et al.
patent: 4237447 (1980-12-01), Clark
patent: 4247892 (1981-01-01), Lawrence
patent: 4251879 (1981-02-01), Clark
patent: 4307446 (1981-12-01), Barton et al.
patent: 4317193 (1982-02-01), Joel, Jr.
patent: 4344134 (1982-08-01), Barnes
patent: 4347498 (1982-08-01), Lee et al.
patent: 4412285 (1983-10-01), Neches et al.
patent: 4417244 (1983-11-01), Melas
patent: 4417245 (1983-11-01), Melas
patent: 4445171 (1984-04-01), Neches
patent: 4456987 (1984-06-01), Wirsing
patent: 4466060 (1984-08-01), Riddle
patent: 4481623 (1984-11-01), Clark
patent: 4484262 (1984-11-01), Sullivan
patent: 4486877 (1984-12-01), Turner
patent: 4491945 (1985-01-01), Turner
patent: 4494185 (1985-01-01), Gunderson et al.
patent: 4518960 (1985-05-01), Clark
patent: 4523273 (1985-06-01), Adams, III et al.
patent: 4540000 (1985-09-01), Bencher
patent: 4543630 (1985-09-01), Neches
patent: 4550397 (1985-10-01), Turner
patent: 4561090 (1985-12-01), Turner
patent: 4577308 (1986-03-01), Larson
patent: 4621359 (1986-11-01), McMillen
patent: 4622632 (1986-11-01), Tanimoto et al.
patent: 4623996 (1986-11-01), McMillen
patent: 4630258 (1986-12-01), McMillen
patent: 4630260 (1986-12-01), Toy et al.
patent: 4633394 (1986-12-01), Georgiou et al.
patent: 4638475 (1987-01-01), Koike
patent: 4651318 (1987-03-01), Luderer
patent: 4656622 (1987-04-01), Lea et al.
patent: 4661947 (1987-04-01), Lea et al.
patent: 4663620 (1987-05-01), Paul et al.
patent: 4670871 (1987-06-01), Vaidya
patent: 4679186 (1987-07-01), Lea
patent: 4695999 (1987-09-01), Lebizay
patent: 4701906 (1987-10-01), Ransom et al.
patent: 4706150 (1987-11-01), Lebizay et al.
patent: 4707781 (1987-11-01), Sullivan
patent: 4731825 (1988-03-01), Wojcinski et al.
patent: 4731878 (1988-03-01), Vaidya
patent: 4734907 (1988-03-01), Turner
patent: 4740954 (1988-04-01), Cotton
patent: 4742511 (1988-05-01), Johnson
patent: 4745593 (1988-05-01), Stewart
patent: 4761780 (1988-08-01), Bingham
patent: 4766534 (1988-08-01), DeBenedictis
patent: 4780873 (1988-10-01), Mattheyses
patent: 4782478 (1988-11-01), Day, Jr. et al.
patent: 4785446 (1988-11-01), Dias et al.
patent: 4809362 (1989-02-01), Claus et al.
patent: 4811210 (1989-03-01), McAulay
patent: 4814973 (1989-03-01), Hillis
patent: 4814979 (1989-03-01), Neches
patent: 4814980 (1989-03-01), Peterson
patent: 4817084 (1989-03-01), Arthurs et al.
patent: 4829227 (1989-05-01), Turner
patent: 4833468 (1989-05-01), Larson et al.
patent: 4833671 (1989-05-01), Becker et al.
patent: 4845722 (1989-07-01), Kent et al.
patent: 4845736 (1989-07-01), Posner et al.
patent: 4845744 (1989-07-01), DeBenedictis
patent: 4847755 (1989-07-01), Morrison et al.
patent: 4849751 (1989-07-01), Barber et al.
patent: 4860201 (1989-08-01), Stolfo et al.
patent: 4864558 (1989-09-01), Imagawa et al.
patent: 4866701 (1989-09-01), Giacopelli et al.
patent: 4925311 (1990-05-01), Neches et al.
patent: 4945471 (1990-07-01), Neches
patent: 4956772 (1990-09-01), Neches
patent: 4962497 (1990-10-01), Ferenc et al.
patent: 5006978 (1991-04-01), Neches
patent: 5022025 (1991-06-01), Urushidani et al.
patent: 5088091 (1992-02-01), Schroeder et al.
patent: 5119369 (1992-06-01), Tanabe et al.
patent: 5121384 (1992-06-01), Ozeki et al.
patent: 5199027 (1993-03-01), Barri
patent: 5214642 (1993-05-01), Kunimoto et al.
patent: 5522046 (1996-05-01), McMillen et al.
R. J. McMillen, A Study of Multistage Interconnection Networks: Design, Distributed Control, Fault Tolerance, and Performance, PhD Thesis, Purdue University, Dec. 1982.
Dr. Philip M. Neches, "THE YNET: An Interconnect Structure for a Highly Concurrent Data Base Computer System", Teradata Corporation, 1988.
R. D. Rettberg, W.R. Crowther, P.P. Carvey and R.S. Tonalanson, "The Monacrch Parallel Processor Hardware Design", Computer, Apr. 1990, pp. 18-30.
L. R. Goke amd G.J. Lipovski, "Banyan Networks for Partitioning Multiprocessor Systems", Processing of the First Annual Symposium on Computer Architecture, 1973, pp. 21-28.
T. Feng, "A Survey of Interconnection Networks", Computer, Dec, 1981, pp. 12-27.
D.P. Agrawal, "Testing and Fault Tolerance of Multistage Interconnection Networks", Computer, Apr. 1982, pp. 41-53.
Burroughs Corporation, "Final Report: Numerical Aerodynamic Simulation Facility; Feasibility Study", Mar. 1979.
G. F. Pfister, W.C. Brantley, D.A. George, S.L. Harvey, W.J. Kleinfelder, K.P. McAuliffe, E.A. Melton, V.A. Norton, and J. Weiss, "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture", Proceedings of the 1985 International Conference on Parallel Processing, 1985, pp. 764-771.
G.F. Pfister and V.A. Norton, "Hot Spot Contention and Combining in Multistage Interconnection Networks", Processings of the 1985 International Conference on Parallel Processing, 1985, pp. 790-797.
W.C. Brantley, K.P. McAuliffe, and J. Weiss, "RP3 Processor-Memory Element", Proceedings of the 1985 International Conference on Parallel Processing, pp. 782-789.
W. Crowther, J. Goodhue, E. Starr, R. Thomas, W. Milliken and T. Blackadar, "Performance Measurements on a 128-node Butterfly.TM. Parallel Processor" Proceedings of the 1985 International Conference on Parallel Processing, 1985, pp. 531-540.
A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph and M. Snir, "The NYU Ultra Computer-Designing an MIMD Shared Memory parallel Computer" IEEE Transactions on Computers, vol. C-32, No. 2, Feb. 1983, pp. 175-189.
Leiserson, "Transactions on Computers," IEEE, vol. C-34, No. 10, Oct. 1985.
Chura David J.
McMillen Robert J.
Watson M. Cameron
Luu Le Hien
NCR Corporation
LandOfFree
Computer system using a master processor to automatically reconf does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer system using a master processor to automatically reconf, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system using a master processor to automatically reconf will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2069402